Abstract: Provided is a method for changing a resolution of an image shown on a display. The method, in one embodiment, includes, providing an image on a display, and detecting a relative distance of an object to the display. The method, in this embodiment, further includes changing a resolution of the image as the relative distance changes.

Abstract: One embodiment of the present invention includes a method for processing graphics objects. The method includes receiving a first draw-call and a second draw-call. The method also includes dividing the first draw-call into a first set of sub-draw-calls and the second draw-call into a second set of sub-draw-calls. The method further includes identifying a first screen tile. The method also includes identifying a first group of sub-draw-calls included in the first set of sub-draw-calls that overlap the first screen tile and a second group of sub-draw-calls included in the second set of sub-draw-calls that overlap the second screen tile. The method further includes causing the first group of sub-draw-calls and the second group of sub-draw-calls to be processed together.

Abstract: A gaming cloud gaming system and a method of initiating a gaming session. One embodiment of the gaming cloud gaming system includes a computing system having: (1) an entry point operable to receive a game session request and generate instructions for establishing a connection between a client and a game server, and (2) a dynamically configurable reverse proxy operable to proxy for the game server and configured to employ the instructions to create a route to a randomly selected port on the game server through which the connection is makeable.

Abstract: One aspect of the present disclosure provides an IC package that includes a printed circuit board (PCB) having a first material layer located thereon. The first material layer has bond pads located therein that form a contact array defined by a perimeter. A second material layer is located at or adjacent an outer edge of the PCB. The second material layer is located outside the perimeter of the contact array and has a higher coefficient of thermal expansion (CTE) value and a greater thickness than the first material layer.

Abstract: A passive stylus with a deformable tip is described herein. In one embodiment, a thin annular body configured to be hand-held with a chisel shaped tip disposed at the first end of the body is provided. The chisel shaped tip includes a deformable material such that the chisel shaped tip is operable to interface with a touch a sensitive surface with a detectable surface area when a first pressure is exerted on the body and translated to the chisel shaped tip. The chisel shaped tip is operable to interface with the touch sensitive surface with a second detectable surface area, this one different from the first detectable surface area, when a second pressure is exerted on the body and translated to the chisel shaped tip. The stylus may include a second tip on the back end for providing an erase function.

Abstract: Methods and systems for maintenance and control of multiple versions of an application are disclosed. The method includes creating a first version of the application comprising computer-executable instructions and executing the first version of the application. The first version of the application and related performance metrics are stored in a memory. The method includes creating at least one modified version of the application by making changes to the computer-executable instructions and executing the modified version of the application. The modified version of the application and related performance metrics are stored in the memory. The method includes comparing the performance of the modified version of the application to the performance of the first version of the application by comparing their respective performance metrics and deleting the lower performing version.

Abstract: A memory driver, a method of driving a command bus for a synchronous dual data rate (sDDR) memory and a memory controller for controlling dynamic random-access memory (DRAM). In one embodiment, the memory driver includes: (1) pull-up and pull-down transistors couplable to a command bus of a memory controller and operable in 1N and 2N timing modes and (2) gear down offset circuitry coupled to the pull-up transistor and operable to offset the command bus when transitioning out of the 1N timing mode and increase an extent and duration of 1-0-1 transitions on the command bus.

Abstract: A computing system and method for automatically making a display configuration persistent. One embodiment of the computing system includes: (1) a video adapter coupled to a data bus and operable to interface a display configuration associated with extended display identification data (EDID), (2) a cache configured to store the EDID, and (3) a central processing unit (CPU) coupled to the data bus and the cache, and operable to execute a driver associated with the video adapter and configured to detect the display configuration and cause the EDID to be written to the cache.

Abstract: A method includes capturing an interaction of a user of a data processing device therewith at a level of a user space through a process executing on the data processing device, and communicating the captured user interaction as an event from the user space to a kernel space associated with an operating system executing on the data processing device. The method also includes incorporating, through the kernel space, the communicated event as a feedback to an algorithm executing on a processor of the data processing device communicatively coupled to a memory. The algorithm is configured to modify a current performance state of the processor based on threshold levels of utilization of the processor. Further, the method includes automatically switching, based on the algorithm execution, the current performance state of the processor to a higher power state or a lower power state thereof additionally in accordance with the communicated event.

Abstract: Methods and apparatus for debugging finite state machine are disclosed. The method includes implementing a debug logic circuit and connecting the debug logic circuit to a system on chip (SoC) voltage source. The method includes operating a finite state machine that sequences the SoC from a low power state to a next low power state and generating respective output signals corresponding to the low power states and wherein the finite state machine is connected to Always On voltage source. The method includes masking the output signals to generate respective masked output signals, and applying the masked output signals to SoC circuit elements to prevent from transitioning into low power states and hence keeping the debug logic circuitry alive. The method includes debugging the finite state machine in the lowest power state by the debug logic circuit.

Abstract: One aspect provides a method for image display. The method for image display, in accordance with one embodiment, includes providing a display, the display having a maximum display area (Amax) defined by a total number of pixels. The method for image display, in accordance with this embodiment, may further include activating, in an attempt to extend battery life, less than all of the total number of pixels of the display to provide a modified display area (Amod) that is less than the maximum display area (Amax).

Abstract: A system, method, and computer program product are provided for scheduling interruptible hatches of instructions for execution by one or more functional units of a processor. The method includes the steps of receiving a batch of instructions that includes a plurality of instructions and dispatching at least one instruction from the batch of instructions to one or more functional units for execution. The method further includes the step of receiving an interrupt request that causes an interrupt routine to be dispatched to the one or more functional units prior to all instructions in the batch of instructions being dispatched to the one or more functional units. When the interrupt request is received, the method further includes the step of storing batch-level resources in a memory to resume execution of the batch of instructions once the interrupt routine has finished execution.

Abstract: Various disclosed embodiments are directed to methods and systems for reducing memory space in sequential computer-implemented operations. The method includes generating a directed acyclic graph (DAG) having a plurality of vertices and directed edges, wherein each edge connects a predecessor vertex to a successor vertex. Each vertex represents one of the computer-implemented operations and each directed edge represents output data generated by the operations. The method includes merging one of the predecessor vertex with one of the successor vertex by combining the operations of the predecessor vertex and the successor vertex if the predecessor and successor vertices are connected by a directed edge and there is only one directed edge originating from the predecessor vertex. The merger of the predecessor and the successor vertices reduces the number of directed edges in the DAG, resulting in a reduction of intermediate buffer memory required to store the output data.

Abstract: A system, method, and computer program product are provided for determining a quantity of light received by an element of a scene. In use, a quantity of light received by a first element of the scene is determined by averaging a quantity of light received by elements of the scene that are associated with a selected set of light paths.

Abstract: A graphics processing subsystem and a method for recovering a video basic input/output system (VBIOS). One embodiment of the graphics processing subsystem includes: (1) a memory configured to store a VBIOS, and (2) a processor coupled to the memory and configured to employ a bridge to gain access to the VBIOS and cause the VBIOS to be written to the memory.

Abstract: A system, method, and computer program product are provided for sensing input stimulus at an input device. The method includes the steps of configuring an input device comprising a first sensor layer and a second sensor layer to activate the first sensor layer and to deactivate the second sensor layer, where the second sensor layer is layered above the first sensor layer and associated with a stimulus device. When a request to activate the second sensor layer is received, the input device is configured to activate the second sensor layer to respond to stimulus received by the stimulus device and to deactivate the first sensor layer. A third sensor layer may be included in the input device and the third sensor layer may be associated with a different stimulus device.

Abstract: Systems and methods are provided for capturing and processing digital images. During a capture session, an image capture system is configured to capture one or more subject images and one or more calibration images potentially containing the user's face under common lighting conditions. The subject images and the calibration images are captured using two differently-aimed cameras within a common enclosure. The one or more calibration images are compared to one or more previously-captured reference images containing the user's face and captured under specified lighting conditions. The comparison yields one or more calibration outputs that are applied to the one or more subject images to generate adjusted subject images, for example, images that have been white-balanced to remove color casts caused by the lighting conditions.

Abstract: A clock signal generation circuit provides an output clock signal to a digital system. The digital system is powered by a power supply voltage, VDD, that may include transients associated with the impedance of the packaged digital system. The clock signal generation circuit dynamically scales an output clock frequency based on monitored changed to VDD. The output clock frequency may be selected to approximate a maximum (margin-less) system Fmax for the monitored VDD. The average clock frequency may be improved compared with operating at a fixed output clock frequency.

Abstract: A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in which the offline RO is disconnected from both the drive voltage source and the clock source, the frozen RO is connected to the drive voltage source but disconnected from the clock source and the online RO is connected to both the drive voltage source and the clock source.

Abstract: A passive stylus with a deformable tip is described herein. In one embodiment, a thin annular body configured to be hand-held with a tip disposed at the first end of the body is provided. The tip includes a deformable material such that the tip is operable to interface with a touch a sensitive surface with a detectable surface area when a first pressure is exerted on the body and translated to the tip. The tip is operable to interface with the touch sensitive surface with a second detectable surface area, this one different from the first detectable surface area, when a second pressure is exerted on the body and translated to the tip. The stylus may include a second tip on the back end for providing an erase function.