Abstract: Embodiments are disclosed relating to an electric power conversion device and methods for controlling the operation thereof. One disclosed embodiment provides a multi-stage electric power conversion device including a first regulator stage including a first stage energy storage device and a second regulator stage including a second stage energy storage device, the second stage energy storage device being operatively coupled between the first stage energy storage device and the load. The device further includes a control mechanism operative to control (i) a first stage output voltage on a node between the first stage energy storage device and the second stage energy storage device and (ii) a second stage output voltage on a node between the second stage energy storage device and the load.

Abstract: A method of detecting an error in a security mode configuration procedure conducted at a radio access network is provided. A cell update message is transmitted which causes the radio access network to abort a security mode configuration procedure. After the transmission of an update message, a new security mode configuration is received and the original security mode configuration is replaced with a new security mode configuration. A security mode configuration check is performed on a received downlink message using the new security mode configuration. If the security mode configuration check fails, a further security mode configuration check is performed on the downlink message to detect an error in the security mode configuration procedure. If it is determined there has been an error in the security mode configuration procedure, security mode configuration checks are performed on further downlink messages received from the network using the original security mode configuration.

Abstract: Methods and systems for reducing or eliminating distortion in an image are described. The approach generally involves determining the distortion introduced by a lens, and modifying a captured image to reduce that distortion. In one embodiment, the distortion information associated with a lens is determined. The distortion information is stored. A captured image taken by that lens is processed, with reference to the distortion information.

Abstract: A processor and a system are provided for performing texturing operations loaded from a texture queue that provides temporary storage of texture coordinates and texture values. The processor includes a texture queue implemented in a memory of the processor, a crossbar coupled to the texture queue, and one or more texture units coupled to the texture queue via the crossbar. The crossbar is configured to reorder texture coordinates for consumption by the one or more texture units and to reorder texture values received from the one or more texture units.

Abstract: A technique for providing electrostatic discharge (ESD) protection in complementary metal-oxide semiconductor (CMOS) technologies is disclosed. A power supply RC-based ESD protection circuit having an RC value in the nanosecond range increases the allowable power-up slew rate so that fast power-up events (e.g., hot-plug and power switching operations) are not erroneously interpreted as ESD events. Because the RC value is small, the layout area needed for the RC-based ESD protection circuit is also reduced.

Abstract: Method including casting a first plurality of rays towards an original 3-D scene comprising objects with object surfaces. Method also includes constructing a simplified representation of the original 3-D scene and adjusting the simplified representation to be consistent with the original 3-D scene. Simplified representation is adjusted by using known rays and object surface intersections obtained from the casting, to produce an adjusted simplified representation.

Abstract: A system and method for re-factorizing a square input matrix on a parallel processor. In one embodiment, the system includes: (1) a matrix generator operable to generate an intermediate matrix by embedding a permuted form of the input matrix in a zeroed-out sparsity pattern of a combination of lower and upper triangular matrices resulting from a prior LU factorization of a previous matrix having a same sparsity pattern, reordering to minimize fill-in and pivoting strategy as the input matrix and (2) a re-factorizer associated with the matrix generator and operable to use parallel threads to apply an incomplete-LU factorization with zero fill-in on the intermediate matrix.

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Abstract: A system, method, and computer program product are provided for translating a hardware design. In use, a hardware design is received that is a graph-based common representation of a hardware design stored in a hardware model database. Logic code is generated for each hardware module node of the graph-based common representation of the hardware design. Additionally, flow control code is generated for each hardware module node of the graph-based common representation of the hardware design. A logic code model of the hardware design that includes the generated logic code and the generated flow control code is stored.

Abstract: Provided is a multi-band antenna. The multi-band antenna, as provided in one embodiment, includes a first resonant portion having a first length defined by an outer perimeter of a conductive segment and operable to effect an antenna for communication in a first band of frequencies. The multi-band antenna, in this aspect, further includes a second resonant portion having a second length defined by an inner perimeter of the conductive segment and operable to resonate capacitively for communication in a second different band of frequencies.

Abstract: Embodiments of the present invention are directed to provide novel methods and a system for adaptive resolution rendering via scaling in a multiple graphics processor system. A method is described herein that maintains a constant framerate by reducing the resolution of the graphical output rendered in one graphics processor and using another graphics processor in the same computing system to scale the already-rendered output to its original intended resolution when the framerate drops below a desired threshold.

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a system function chip, and an MCM package configured to include the first processor chip and the system function chip. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The system function chip is configured to include a second GRS interface circuit. A first set of electrical traces are fabricated within the MCM package and coupled to the first GRS interface circuit and to the second GRS interface circuit. The first GRS interface circuit and second GRS interface circuit together provide a communication channel between the first processor chip and the system function chip.

Abstract: A method and apparatus for performing display image refresh in bursts to a display device. A buffered refresh controller includes capabilities to drive the display based on video signals generated from a local frame buffer at a first rate. The graphics controller may optimally be configured to burst a new frame of pixel data to the buffered refresh controller at a second rate to replace the previous frame of pixel data in the local frame buffer. The second rate is different than the first rate. Additionally, the graphics controller may send frames only when they contain new pixel data. By enabling the graphics controller to selectively transmit the new frame of pixel data at the second rate, higher than the first rate, the graphics controller may be placed in a power-saving state during at least a portion of each frame update.

Abstract: A system, method, and computer program product are provided for copying data between memory locations. In use, a memory copy instruction is implemented. Additionally, data is copied from a first memory location to a second memory location, utilizing the memory copy instruction.

Abstract: The present invention sets forth a method for supporting enhanced audio on a graphics processing unit (GPU) in a computing device having a graphics subsystem. In one embodiment, the method includes the steps of determining whether an option of a GPU audio output is enabled and the graphics subsystem and a first external output device is connected, and routing a first audio stream to the GPU of the graphics subsystem for processing when the option of the GPU audio output is enabled and the graphics subsystem and the first external output device is in connection and causing the processed first audio stream to be transferred along a first transmission path to the first external output device, or otherwise causing a second audio stream to be transferred along a second transmission path to a second external output device.

Abstract: A processor and a system are provided for performing texturing operations. The processor includes a texture return buffer having a plurality of slots for storing texture values and one or more texture units coupled to the texture return buffer. Each of the slots of the texture return buffer are addressable by a thread. Each texture unit is configured to allocate a slot of the texture return buffer when the texture unit generates a texture value.

Abstract: Embodiments of the invention generally include apparatus for providing a positive locked connection for I/O devices to computing devices. In one embodiment, an external latching apparatus for an Input/Output (I/O) connection is provided. The external latching apparatus includes a main body and at least one latch. The main body includes a first surface configured to abut to an I/O card bracket and a second surface, parallel and spaced apart from the first surface. The at least one latch extends from the main body beyond the first surface. A plurality of parallel slots are formed in the second surface. Each slot is open on a bottom side of the body and is configured to receive a cable of an I/O cable assembly.

Abstract: A method and a system are provided for clock phase detection. A set of delayed versions of a first clock signal is generated. The set of delayed versions of the first clock is used to sample a second clock signal, producing a sequence of samples in a domain corresponding to the first clock signal. At least one edge indication is located within the sequence of samples.

Abstract: The presentation of stereoscopic display content for viewing with passive glasses and full resolution is provided. In use, (a) a frame of stereoscopic display content intended for viewing by one eye of a user is scanned, using a display layer of a display device; (b) the scanned frame is polarized utilizing a polarizing layer of the display device, according to a polarization associated with a lens of stereoscopic glasses worn over the same one eye of the user; (c) a backlight is activated to illuminate the polarized frame, in response to an entirety of the polarized frame being scanned; (d) the display device is held for a predetermined period of time in response to activation of the backlight, and then the backlight is de-activated; and (a)-(d) are then repeated for the other eye of the user, with another frame of stereoscopic display content intended for viewing by the other eye.

Abstract: Methods and apparatus for providing additional storage, in the form of a hardware assisted stack, usable by software running an environment with limited resources. As an example, the hardware assisted stack may provide additional stack space to VBIOS code that is accessible within its limited allocated address space.