Abstract: In some embodiments, a notebook including a main display, a main graphics subsystem, and an auxiliary display subsystem, but typically not an auxiliary display, wherein the notebook is configured to display on the main display one or both of data from the auxiliary display subsystem (or a scaled or otherwise processed version of such data), and data from the main graphics subsystem. Preferably, the notebook is configured to display a scaled version of data from the auxiliary display subsystem on part of the main display's screen. Other embodiments are timing controllers and other circuitry for use in such a notebook and methods for displaying data from such a notebook's auxiliary display subsystem on all or part of the main display's screen. The notebook can include a timing control subsystem for asserting to the main display one or both of display data from the auxiliary display subsystem (or a processed version thereof) and display data from the main graphics subsystem.

Abstract: Synthesizable code representing first-in-first out (FIFO) memories may be used to produce FIFO memories in a hardware element or system. To more efficiently use a memory element that stores the data in a FIFO, a code generator may generate a wrapper that enables the FIFO to use a memory element with different dimension (i.e., depth and width) than the FIFO's dimensions. For example, the wrapper enables a 128 deep, 1 bit wide FIFO to store data in a memory element with 16 rows that store 8 bits each. To any system communicating with the FIFO, the FIFO behaves like a 128×1 FIFO even though the FIFO is implemented using a 16×8 memory element. To do so, the code generator may generate a wrapper which enables the folded memory element to behave like a memory element that was not folded.

Abstract: One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system performance. A credit-based technique may be used to control instruction by instruction scheduling for each warp in a group so that the group of warps is processed uniformly. A credit is computed for each warp and the credit contributes to a weight for each warp. The weight is used to select instructions for the warps that are issued for execution.

Abstract: A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.

Abstract: One embodiment of the present invention sets forth a method for managing a power state of an audio device resident in a graphics processing unit. The method includes the steps of directing audio data originated from a client application via an audio path in an audio driver stack to the audio device, determining whether an active stream of audio data along the audio path is present in response to a notification of an attempt to shut down the graphics processing unit, and requesting a plug and play manager to disable the audio device, if no active stream of audio data is present along the audio path.

Abstract: A backward-compatible stereo image processing system and a method of generating a backward-compatible stereo image. One embodiment of the backward-compatible stereo image processing system includes: (1) first and second viewpoints for an image, (2) an intermediate viewpoint for the image, and (3) first and second output channels configured to provide respective images composed of high spatial frequency content of the intermediate viewpoint and respective low spatial frequency content of the first and second viewpoints.

Abstract: A method includes triggering, through an interface of a data processing device, cropping of a display screen area of a display unit of the data processing device. The method also includes initiating, through a driver component associated a processor of the data processing device, an operating system executing on the data processing device and/or an application executing on the data processing device, the processor to process pixel data to be displayed on the display screen area based on the triggering. Further, the method includes rendering, through the processor, the processed pixel data on a cropped portion of the display screen area of the display unit.

Abstract: One embodiment provides a data-receiving device component comprising a phase shifter, timer logic, and control logic. The phase shifter is configured to release a train of clock pulses with a controlled phase shift. The timer logic is configured to receive data from a data-sending device, and for each transition of the data received, to determine whether a clock pulse from the train is early or late with respect to the transition, and to tally the late clock pulses relative to the early clock pulses. The control logic, operatively coupled to the phase shifter and to the timer logic, is configured to incrementally advance the phase shift when the late clock pulses outnumber the early clock pulses by a non-integer power of two.

Abstract: A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.

Abstract: One embodiment of the present invention sets forth a technique for specifying scene programs, where the effect of executing a particular scene program is to generate a sequence of graphics commands. The application programming interface is extended to include calls used to specify a high-level scene program. Upon receiving a high-level scene program, the graphics driver generates a machine code scene program. When an application program emits a call to execute one or more machine code scene programs, the graphics driver transmits corresponding scene programs execution commands to the graphics pre-processing unit. For each scene program execution command, the graphics pre-processing unit processes instructions, programmatically reconfigures the graphics pipeline based on the execution of the machine code scene program, and launches one or more parallel threads that execute commands within the graphics pipeline.

Abstract: A method in system for latency buffered scoreboarding in a graphics pipeline of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality pixels related to the graphics primitive. An ID stored to account for an initiation of parameter evaluation for each of the plurality of pixels as the pixels are transmitted to a subsequent stage of the graphics processor. A buffer is used to store the fragment data resulting from the parameter evaluation for each of the plurality of pixels by the subsequent stage. The ID and the fragment data from the buffering are compared to determine whether they correspond to one another. The completion of parameter evaluation for each of the plurality of pixels is accounted for when the ID and the fragment data match and as the fragment data is written to a memory.

Abstract: A technique for efficiently rendering content reduces each complex blend mode to a series of basic blend operations. The series of basic blend operations are executed within a recirculating pipeline until a final blended value is computed. The recirculating pipeline is positioned within a color raster operations unit of a graphics processing unit for efficient access to image buffer data.

Abstract: The invention provides a method for driving a graphic processing unit (GPU), where a driver applies two threads to drive one ore more GPUs. The method includes the steps of: (a) activating a rendering thread and a displaying thread in response to invoking by an application thread of a graphics application; (b) sending according to the rendering thread a plurality of rendering instructions for enabling generation of at least a first rendered frame and a second rendered frame; and (c) sending according to the displaying thread one or more interpolating instructions and one or more displaying instructions, the one or more interpolating instructions enabling execution of interpolation according to the at least a first rendered frame and the second rendered frame to create one or more interpolated frames, and the one or more displaying instructions enabling display of the one or more interpolated frames.

Abstract: Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS switch device serially coupled to a second NMOS switch device. In this embodiment, the gate node of the first NMOS switch device is coupled to the word line, a source node of the first NMOS switch device is coupled to the cross-coupled data latch, a gate node of the second NMOS switch device is coupled to the write column select line, and a source node of the second NMOS switch device is coupled to the cross-coupled data latch.

Abstract: Embodiments of the claimed subject matter are directed to systems and a method that allows the aggregation of multiple interfaces of a single data communication bus to provide greater bandwidth for communication between a peripheral device and system memory within a computing system. In one embodiment, a system is provided wherein the unoccupied interfaces of the data communication bus is aggregated with an occupied interface coupled to a peripheral device to increase the bandwidth of data transfer requests between the peripheral device and the system memory.

Abstract: A system, method, and computer program product are provided for generating unique primitive identifiers. A specified scope and geometry for a scene is received. A primitive identifier is generated for each primitive of a particular type, where each of the primitive identifiers is unique within the specified scope, and where the primitives are generated as the geometry for the 3D graphics scene is processed by a graphics processing unit. Different types may include patches, triangles, and vertices. The specified scope may be one of a frame, region, pixel, or draw call.

Abstract: The present invention facilitates efficient and effective detection of pixel alteration. The number and configuration of pixels in a block partition can be flexibly changed. The filter inputs in the multi-protocol filter can be flexibly changed to meet the deblocking requirement in the target video compression standard. In one embodiment, the deblock engine includes an input interface, a neighbor buffer, a current data buffer; and a multi-protocol filter. The input interface receives reconstructed data. The neighbor buffer temporarily stores neighbor information. The current data buffer receives the reconstructed data and the neighbor information. The multi-protocol filter filters information selected from the reconstructed data and neighbor information.

Abstract: Methods for code protection are disclosed. A method includes using a security processing component to access an encrypted portion of an application program that is encrypted by an on-line server, after a license for use of the application program is authenticated by the on-line server. The security processing component is used to decrypt the encrypted portion of the application program using an encryption key that is stored in the security processing component. The decrypted portion of the application program is executed based on stored state data. Results are provided to the application program that is executing on a second processing component.

Abstract: A technique for enhancing the efficiency and speed of data transmission within and across multiple, separate computer systems includes the use of an MPI library/engine. The MPI library/engine is configured to facilitate the transfer of data directly from one location to another location within the same computer system and/or on separate computer systems via a network connection. Data stored in one GPU buffer may be transferred directly to another GPU buffer without having to move the data into and out of system memory or other intermediate send and receive buffers.

Abstract: A system includes a processor having an instruction register for storing an instruction having a predefined opcode, a predicate register for storing a predicate condition to select an output register for a result of the instruction, a first output register, and a second output register. The processor further includes processor circuitry operable to execute the instruction to produce a result, and processor circuitry operable to store the result of the instruction in the first output register if the predicate condition to select the output is true, and to store the second output register if the predicate condition to select the output is false. A single instruction is used to produce the result, and to store the result of the instruction.