Abstract: The graphics processing technique includes detecting a transition from rendering graphics on a first graphics processing unit to a second graphics processing, by a hybrid driver. The hybrid driver, in response to detecting the transition, configures the first graphics processing unit to create a frame buffer. Thereafter, an image rendered on the second graphics processing unit may be copied to the frame buffer of the first graphics processing unit. The rendered image in the frame buffer may then be scanned out on the display.

Abstract: A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

Abstract: A system, process, and computer program product are provided for sampling a hierarchical depth map. An approach for sampling the hierarchical depth map includes the steps of generating a hierarchical depth map and reading a value associated with a sample pixel from a target level of the hierarchical depth map based on a difference between the sample pixel and a target pixel. The hierarchical depth map includes at least two levels.

Abstract: A dynamic AC prediction technique is implemented in a data partition mode which automatically disables AC prediction for encoding the current macroblock in the next packet when packet overflow occurs. Otherwise, when there is no overflow, AC prediction remains enabled to maintain compression efficiency. More particularly, in the preferred embodiment, a determination is first made whether a macroblock causes a packet overflow if it is encoded in the current packet. If so, a new packet is initiated into which the macroblock is encoded without AC prediction as the first macroblock. Otherwise, the macroblock with AC prediction remains in the current packet and a new macroblock is encoded.

Abstract: A method for managing memory traffic includes causing first data to be written to a data cache memory, where a first write request comprises a partial write and writes the first data to a first portion of the data cache memory, and further includes tracking the number of partial writes in the data cache memory. The method further includes issuing a fill request for one or more partial writes in the data cache memory if the number of partial writes in the data cache memory is greater than a predetermined first threshold.

Abstract: A tessellation pipeline includes an alpha phase and a beta phase. The alpha phase includes pre-tessellation processing stages, while the beta phase includes post-tessellation processing stages. A processing unit configured to implement a processing stage in the alpha phase stores input graphics data within a buffer and then copies over that buffer with output graphics data, thereby conserving memory resources. The processing unit may also copy output graphics data directly to a level 2 (L2) cache for beta phase processing by other tessellation pipelines, thereby avoiding the need for fixed function copy-out hardware.

Abstract: A method for using a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor. For each of the read requests, a determination is made as to whether there is a cache line hit corresponding to the request. For each cache line miss, a cache line slot is allocated to store a new cache line responsive to the cache line miss. An in-order set of cache lines is output to the video processor responsive to the queue of read requests.

Abstract: One embodiment of the present invention sets forth an improved way to prefetch instructions in a multi-level cache. Fetch unit initiates a prefetch operation to transfer one of a set of multiple cache lines, based on a function of a pseudorandom number generator and the sector corresponding to the current instruction L1 cache line. The fetch unit selects a prefetch target from the set of multiple cache lines according to some probability function. If the current instruction L1 cache 370 is located within the first sector of the corresponding L1.5 cache line, then the selected prefetch target is located at a sector within the next L1.5 cache line. The result is that the instruction L1 cache hit rate is improved and instruction fetch latency is reduced, even where the processor consumes instructions in the instruction L1 cache at a fast rate.

Abstract: A transceiver, a method of providing multiple-band virtual concurrent wireless communication and a wireless device incorporating the transceiver or the method. In one embodiment, the transceiver includes: (1) first transmit and receive intermediate frequency (IF) strips, (2) second transmit and receive IF strips, (3) first and second local oscillators (LOs) and (4) switches operable to multiplex clock signals from the first and second local oscillators to cause the transceiver to operate in a selectable one of: (4a) a unified, multiple-input, multiple-output (MIMO) mode in which the first and second transmit and receive IF strips are driven to transmit and receive in a first band and (4b) a concurrent multiple-band connection mode in which the first transmit and receive IF strips are driven in the first band and the second transmit and receive IF strips are concurrently driven in a second band.

Abstract: A method for angularly varying backlight illumination of a backlit display device. The method comprises determining at least one subject position and angularly varying a backlight illumination of a displayed image. The backlight illumination is angularly varied based upon and directed towards a determined position of the at least one subject. The angularly varied backlight illumination of the displayed image reduces the backlight illumination of the displayed image that is visible outside of the determined position of the at least one subject.

Abstract: A method includes automatically capturing, through a processor of a data processing device communicatively coupled to a memory, one or more parameter(s) related to a visual quality of rendering of a video frame that is part of a sequence on a display unit communicatively coupled to the processor and one or more parameter(s) related to latency associated with the rendering of the video frame on the display unit. The sequence is a video and/or a graphics sequence. The method also includes performing, through the processor, an automatic trade-off between the one or more parameter(s) related to the visual quality and the one or more parameter(s) related to the latency to maintain the one or more parameter(s) related to the visual quality or the one or more parameter(s) related to the latency within a threshold during the rendering of the video frame.

Abstract: A method for generating images. The method includes capturing first image data representing a first scene taken optically at a first magnification index, wherein the first image data comprises a first region of an image. The method includes capturing second image data representing a second scene taken optically at a second magnification index that is less than the first magnification index, wherein the second image data comprises a second region of the image. The method includes digitally zooming the second image data in the second region to the first magnification index. The method includes digitally stitching the second image data in the second region to the first image data in the first region.

Abstract: A liquid crystal display (LCD) overdrive interpolation circuit and method, and an LCD drive system incorporating the circuit or method. In one embodiment, the circuit includes: (1) a diagonal interpolator operable to perform a diagonal interpolation along a diagonal direction in a lookup table based on TO and FROM gray levels and (2) a further interpolator coupled to the diagonal interpolator and operable to perform a further interpolation based on a result of the diagonal interpolation and the FROM gray level.

Abstract: A system and method of producing a frame of a video image from an interlaced field. In one embodiment, the method includes: (1) creating an equal-intensity trace from present samples in the field, (2) recognizing an equal-intensity path in the equal-intensity trace, (3) at least partially straightening the equal-intensity path and (4) using the equal-intensity path to determine an intensity value for a missing sample in the frame.

Abstract: One embodiment of the present invention sets forth a technique for performing an intra search. The technique includes performing a first intra search based on a first block size associated with a first pixel block included in a video frame to determine a first intra mode. The technique further includes reconstructing the first pixel block based on the first intra mode to generate reconstructed pixel data. The technique further includes performing, based on the reconstructed pixel data, a second intra search based on a second block size associated with a second pixel block included in the video frame. The second block size is smaller than the first block size. The technique further includes determining a second intra mode based on the second intra search. Advantageously, the disclosed technique enables an intra search to be performed based on a previous intra search size, enabling intra searches to be performed in parallel.

Abstract: A gated divider circuit includes a windowing unit configured to generate windowing waveforms from input oscillator waveforms having a fixed duty cycle. Additionally, the gated divider circuit includes a gated output unit coupled to the windowing unit and configured to provide selected ones of the input oscillator waveforms as controlled by corresponding selected ones of the windowing waveforms. Also included are a method of operating a gated divider circuit and a frequency conversion system employing a gated divider circuit as a local oscillator divider.

Abstract: A system and method for power management by providing advance notice of events. The method includes snooping a register of an operating system timer to determine a timer period associated with a scheduled event. A unit of a computer system is identified that is in a low power state. A wake up latency of the unit is determined that is based on the low power state. An advance period is determined based on the wake up latency. An advance notice of the operating system timer is triggered based on the timer period and the advance period to wake up the unit.

Abstract: A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.

Abstract: An external latching mechanism for an Input/Output (I/O) connection between devices is provided. In one embodiment, an external latching mechanism for an Input/Output (I/O) cable is provided. The external latching mechanism includes a housing coupled to an I/O cable at a first end and having an I/O connector extending a second end. An external latch is coupled by a mounting portion to the housing. The external latch has a first end and a second end. The second end of the arm extends beyond the second end of the housing to a barb. In another embodiment, an external latching Input/Output (I/O) connection is provided that includes a I/O card latching bracket configured to mate with an I/O cable assembly.

Abstract: One embodiment sets forth a technique for deterministic synchronization of signals that are transmitted between different clock domains. The relative phase difference between a source clock domain and a destination clock domain is characterized and the source clock and/or the destination clock are delayed as needed to generate phase-shifted versions of the source and destination clocks for use during a deterministic operating mode. The phase-shifted versions of the source and destination clocks are non-overlapping, meaning that the rising edge of the destination clock does not occur when the source clock is asserted. The non-overlapping source and destination clocks are used by a deterministic synchronization unit to ensure that signals being transmitting from the source clock domain to the destination clock domain are not sampled within a metastability window.