Abstract: A system, method, and computer program product are provided for implementing a storage array. In use, a storage array is implemented utilizing static random-access memory (SRAM). Additionally, the storage array is utilized in a multithreaded architecture.

Abstract: A system, method, and computer program product are provided for determining that a display device is operating in a three-dimensional mode. Further, in response to the determination that the display device is operating in the three-dimensional mode, determining a phase of a current frame. Additionally, a setting from a first table or a setting from a second table is applied based on the determined phase of the current frame.

Abstract: A system, method, and computer program product are provided for determining that a display device is operating in a three-dimensional mode. Further, in response to the determination that the display device is operating in the three-dimensional mode, inverting a polarity of each cell of the display device every N number of frames. Additionally, the N number of frames is even and includes at least two frames.

Abstract: A method includes calculating, through a processor of a computing device communicatively coupled to a memory, correlation between two portions of an image and/or a video frame on either side of a reference portion thereof. The method also includes determining, through the processor, whether content of the image and/or the video frame is stereoscopic or non-stereoscopic based on the determined correlation.

Abstract: A method and system for a cooperative graphics processing across a graphics bus in a computer system. The system includes a bridge coupled to a system memory via a system memory bus and coupled to a graphics processor via the graphics bus. The bridge includes a fragment processor for implementing cooperative graphics processing with the graphics processor coupled to the graphics bus. The fragment processor is configured to implement a plurality of raster operations on graphics data stored in the system memory.

Abstract: A computer system comprising a graphics processor, a frame buffer, a display device, a system agent operable to detect an absence of active software applications and system configurations capable of rendering a disruptive user experience during system suspend, and a memory for storing instructions, that when executed perform a method of entering a power conservation state. The method comprises detecting a system idle event, activating the frame buffer, and storing display information in the frame buffer from the graphics processor. The method further comprises initiating a power reduction state for the graphics processor, self-refreshing the display device during the power reduction state with the display information stored in the frame buffer, and initiating a system suspend comprising a power reduction state for the computer system provided the system agent detects the absence of disruptive software and system configurations.

Abstract: In a CDMA system (100), two chip rates in a TDD cell are supported by: transmitting signals in the system in a frame (400) having a plurality of timeslots; operating at least a first one (0-8) of the plurality of timeslots in the frame at a lower chip rate; and operating at least a second one (9-14) of the plurality of timeslots in the frame at a higher chip rate. This provides the following advantages: provides backwards compatibility of a network including higher chip rate functionality with existing lower chip rate user equipment; allows greater network capacity during the transition phase from a low chip rate network to a high chip rate network; and allows a network operator with a high chip rate network to provide service to roaming users from low chip rate networks.

Abstract: A system, method, and computer program product are provided for testing device parameters. In use, a plurality of device parameters is determined, utilizing a directed acyclic graph (DAG). Further, the determined plurality of device parameters is tested.

Abstract: Provided is an antenna system. The antenna system, in this aspect, includes a loop antenna element, the loop antenna element having a positive loop antenna terminal end and a negative loop antenna terminal end. The antenna system, in this embodiment, further includes an inverted-F antenna element co-located with the loop antenna element, the inverted-F antenna element having a positive inverted-F antenna terminal end and a negative inverted-F antenna terminal end located proximate the positive loop antenna terminal end and the negative loop antenna terminal end. In this antenna system embodiment, the positive loop antenna terminal end, negative loop antenna terminal end, positive inverted-F antenna terminal end and negative inverted-F antenna terminal end alternate between positive and negative terminals.

Abstract: Provided is an antenna. The antenna, in this aspect, includes an inverted-F GPS antenna structure, the inverted-F GPS antenna structure embodying a GPS feed element, a GPS extending arm, and a ground element. The antenna, in this aspect, further includes a loop WiFi antenna structure, the loop WiFi antenna structure embodying a WiFi feed element, the ground element, and a WiFi connecting arm coupling the WiFi feed element to the ground element. In this particular aspect, the ground element is located between the GPS feed element and the WiFi feed element.

Abstract: One embodiment of the present invention sets forth a technique for reducing flicker in image frames captured with a rolling shutter. A flicker detection and correction engine selects a first channel from a first image frame for processing. The flicker detection and correction engine subtracts each pixel value in the first channel from a corresponding pixel value in a prior image frame to generate a difference image frame. The flicker detection and correction engine identifies a first alternating current (AC) component based on a discrete cosine transform (DCT) associated with the difference image frame. The flicker detection and correction engine reduces flicker that is present in the first image frame based on the first AC component. One advantage of the disclosed techniques is that the flicker resulting from fluctuating light sources is correctly detected and reduced or eliminated irrespective of the frequency of the fluctuating light source.

Abstract: When a computing system is running at a lower clock rate, in response to an event that triggers the computing system to increase the clock rate, a list of threads pending execution by the computing system is accessed. The list includes a thread that, when executed, causes the clock rate to increase. That thread is selected and executed before any other thread in the list is executed.

Abstract: A system and method are provided for generating an adaptive clock signal, configured to track prevailing operating conditions within an integrated circuit. The method comprises transmitting a first signal edge to a row of cells within a memory instance, waiting for two or more selected cells within the row of cells to propagate corresponding responses based on the first signal edge, and generating a memory delay signature signal edge based on the corresponding responses. The adaptive clock signal is generated based on the delay signature signal edge.

Abstract: One embodiment of the present invention sets forth a method for causing thread convergence. The method includes determining that a control flow graph representing a first section of a program includes at least two non-overlapping paths that extend from a first divergent node to a candidate node. The method also includes determining that the first divergent node is not a dominator of the candidate node or that the candidate node is not a post-dominator of the first divergent node. The method further includes identifying an external node and inserting a first instruction configured to cause a predicate variable to be set to true for a first set of threads that is to execute the external node. The method additionally includes inserting into the program a second divergent node configured to cause various threads to execute or not execute a first control flow path associated with the external node.

Abstract: A system, method, and computer program product are provided for executing casting-arithmetic instructions. The method comprises receiving a casting-arithmetic instruction that specifies an arithmetic operation to be performed on input data and at least one casting operation of an input casting operation and an output casting operation. Upon determining that the casting-arithmetic instruction specifies the input casting operation, the input casting operation is performed on identified terms comprising the input data. Then the arithmetic operation is performed on the input data to generate an arithmetic result. Upon determining that the casting-arithmetic instruction specifies the output casting operation, the output casting operation is performed on the arithmetic result.

Abstract: A technique of implementing on-screen gestures associated with a software application comprises receiving a first control input that relates to a first scene associated with the software application, translating the first control input into a first set of instructions based on a first mapping, and providing the first set of instructions to an operating system that includes the first set of instructions in the software application, receiving a second control input that relates to a second scene associated with the software application, translating the second control input into a second set of instructions based on a second mapping, and providing the second set of instructions to the operating system, wherein the operating system is configured to include the second set of instructions in the software application.

Abstract: Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.

Abstract: In one embodiment of the present invention, a streaming multiprocessor (SM) uses a tree of nodes to manage threads. Each node specifies a set of active threads and a program counter. Upon encountering a conditional instruction that causes an execution path to diverge, the SM creates child nodes corresponding to each of the divergent execution paths. Based on the conditional instruction, the SM assigns each active thread included in the parent node to at most one child node, and the SM temporarily discontinues executing instructions specified by the parent node. Instead, the SM concurrently executes instructions specified by the child nodes. After all the divergent paths reconverge to the parent path, the SM resumes executing instructions specified by the parent node. Advantageously, the disclosed techniques enable the SM to execute divergent paths in parallel, thereby reducing undesirable program behavior associated with conventional techniques that serialize divergent paths across thread groups.

Abstract: A method of forming a package on package, semiconductor package arrangement is described. In one aspect, solder bumps on a lower surface of a first grid array package substrate are fused to corresponding unencapsulated solder bumps on an upper surface of a second grid array package substrate. The fused solder bumps form solder joints that electrically connect the first and second packages. The height of the resulting solder joints is greater than a height of a die that is flip chip mounted to the second substrate such that the first substrate does not contact any portion of the second package and an air gap is formed that separates the second die from the first package. Corresponding PoP packages structures are also described.

Abstract: Provided is an antenna. The antenna, in one embodiment, includes a feed element having a first feed element end and a second feed element end, the first feed element end configured to electrically connect to a positive terminal of a transmission line. The antenna, in this embodiment, further includes a ground element having a first ground element end and a second ground element end, the first ground element end configured to electrically connect to a negative terminal of the transmission line. In this particular embodiment, the first ground element end is located proximate and inside the first feed element end, and the second ground element end is located proximate and outside the second feed element end.