Abstract: A dynamic multiple input rail switching unit includes a plurality of DC input voltage rails and a rail switching section coupled to the plurality of DC input voltage rails that is configured to individually connect selected ones of the plurality of DC input voltage rails to a switched rail output. The dynamic multiple input rail switching unit also includes a rail selection section that is coupled to the rail switching section and configured to dynamically choose the selected ones by balancing rail supply currents from the plurality of DC input voltage rails based on rail supply current capacity margins and a switched rail output current. A dynamic multiple input rail switching unit operating method, and a dynamic multiple input rail power converter are also provided.

Abstract: A microelectronic package includes larger diameter solder bumps and smaller diameter solder bumps for coupling an interposer to a packaging substrate. The larger diameter solder bumps are positioned on a peripheral surface of the interposer and the smaller diameter solder bumps are positioned on a center surface of the interposer. The solder bumps positioned in the peripheral region can more reliably withstand the higher mechanical stresses that occur in this peripheral region during operation of the microelectronic package.

Abstract: A system, method, and computer program product for applying a spatially varying unsharp mask noise reduction filter is disclosed. The spatially varying unsharp mask noise reduction filter generates a low-pass filtered image by applying a low-pass filter to a digital image, generates a high-pass filtered image of the digital image, and generates an unsharp masked image based on the low-pass filtered image and the high-pass filtered image. The filter also blends the low-pass filtered image with the unsharp masked image based on a shaping function.

Abstract: A sampler circuit for a decision feedback equalizer and a method of use thereof. One embodiment of the sampler circuit includes: (1) a first sampler portion including a series-coupled first master regeneration latch and first slave latch, (2) a second sampler portion including a series-coupled second master regeneration latch and second slave latch, and (3) a first feedback circuit coupled to a first node between the first master regeneration latch and the first slave latch and operable to provide a feedback signal to the second master regeneration latch to cause a bias charge to be built up therefor.

Abstract: Method and apparatus for processing a signal using a recursive method for determining a plurality of frequency components of the signal, the signal being a chirp-like polyphase sequence, wherein a first frequency component of the plurality of frequency components is determined; a component factor is determined by accessing a factor table for use in determining a second frequency component of the plurality of frequency components; and the second frequency component is determined using the determined first frequency component and the determined component factor.

Abstract: Disclosed are a method and system to reduce impedance of printed circuit boards through an interconnecting of printed circuit boards using a square wave pattern of plated-through holes. A method of connecting a first printed circuit board to a second printed circuit board comprises forming a square wave pattern of the first printed circuit board and the second printed circuit board and adjoining the first printed circuit board and the second printed circuit board. The method also involves producing plated-through holes along the square wave pattern, a top section, and/or a bottom section of the adjoined first printed circuit board and second printed circuit board. The method further involves securing the top section and the bottom section using a first metal clip and a second metal clip, respectively, and connecting the first printed circuit board to the second printed circuit board by a wave soldering process.

Abstract: Techniques are disclosed for dispatching pixel information in a graphics processing pipeline. A fragment processing unit in the graphics processing pipeline generates a pixel that includes multiple samples based on a portion of a graphics primitive received by a thread. The fragment processing unit calculates a set of source values, where each source value corresponds to a different sample of the pixel. The fragment processing unit retrieves a set of destination values from a render target, where each destination value corresponds to a different source value. The fragment processing unit blends each source value with a corresponding destination value to create a set of final values, and creates one or more dispatch messages to store the set of final values in a set of output registers. One advantage of the disclosed techniques is that pixel shader programs perform per-sample operations with increased efficiency.

Abstract: Disclosed are methods, an apparatus and a system of automatic topology configuration through automatic profiles across multiple display units. A method of a display driver involves automatically identifying a hardware profile data associated with a plurality of display units, applying a logic function to the hardware profile data to create a set of automatic topology display settings when a match of the hardware profile data with a set of settings in a hardware profile lookup table is not found, and automatically applying the set of automatic topology display settings to simultaneously display a sequence of graphics signals across the plurality of display units. The method may also include automatically designating one display unit from the plurality of display units as a sample display unit and setting a scaling factor based on an automatic designation of the one display unit from the plurality of display units as the sample display unit.

Abstract: A method for compressing normal maps in a computer system. The method includes accessing a map of input normals. A memory block having a first portion and a second portion is defined. A table of indices is stored in the first portion of the memory block and a table of normals is stored in the second portion of the memory block. The indices of the first portion of the memory block reference the normals of the second portion. The normals in the second portion of the memory block are unit normals of a sphere defined to represent the map of input normals.

Abstract: One embodiment of the present invention sets forth a technique for generating a transparency effect for a computing device. The technique includes transmitting, to a camera, a synchronization signal associated with a refresh rate of a display. The technique further includes determining a line of sight of a user relative to the display, acquiring a first image based on the synchronization signal, and processing the first image based on the line of sight of the user to generate a first processed image. Finally, the technique includes compositing first visual information and the first processed image to generate a first composited image, and displaying the first composited image on the display.

Abstract: A method for driving a display panel having a variable refresh rate is disclosed. The method comprises detecting a condition that results in a charge accumulation in the display panel using an accumulated difference in time duration between frames of positive polarity and frames of negative polarity received from an image source. The DC imbalance is a result of a frame pattern comprising alternating frames of differing polarities, wherein frames of positive polarity within the frame pattern are of a different time duration than frames of negative polarity, and wherein the frame pattern results in an accumulation of charge in pixels of the display panel. The method also comprises correcting for the charge accumulation by disrupting the frame pattern.

Abstract: A method for switching, including initializing an instantiation of an application and performing graphics rendering to generate a plurality of rendered frames through execution of the application in order to generate a first video stream comprising the plurality of rendered frames. The method includes sequentially loading the plurality of rendered frames into one or more frame buffers, and determining when a first bitmap of a frame that is loaded into a corresponding frame buffer matches an application signature comprising a derivative of a master bitmap associated with a keyframe of the first video stream.

Abstract: A method includes implementing a cluster computing system including a number of data processing devices coupled to one another in a daisy-chain configuration and communicatively coupled to a server, executing a process on the server and executing an instance of the process on each data processing device. The method also includes remotely configuring, through the server, one or more specific parameter(s) of a display unit associated with a first data processing device, a screen of the display unit, a processor thereof, a memory communicatively coupled to the processor, an algorithm executing thereon and/or a power supply of the first data processing device based on the execution of the process. Further, the method includes remotely configuring, through the server, a same one or more specific parameter(s) associated with a sequentially next data processing device of the cluster computing system based on the remote configuration associated with the first data processing device.

Abstract: A four cycle fused floating point multiply-add unit includes a radix 8 Booth encoder multiplier that is partitioned over two stages with the compression element allocated to the second stage. The unit further includes an improved shifter design. Processing logic analyzes the input operands, detects values of zero and one, and inhibits portions of the processing logic accordingly. When one of the multiplicand inputs has a value of zero or one, the required multiplication becomes trivial, and the unit inhibits the associated coding logic and data transfer to reduce power consumption. The unit then performs an add-only operation. When the addend input has a value of zero, the addition becomes trivial, and the unit inhibits the improved shifter and data transfer to further reduce power consumption. The unit then performs a multiply-only operation.

Abstract: A system and apparatus are provided that include an implementation for decoupled pipelines. The apparatus includes a scheduler configured to issue instructions to one or more functional units and a functional unit coupled to a queue having a number of slots for storing instructions. The instructions issued to the functional unit are stored in the queue until the functional unit is available to process the instructions.

Abstract: An image capturer for reducing the effect of shutter shake of a digital camera in a smartphone, a method of capturing an image employing a digital camera, and a smartphone. In one embodiment, the image capturer includes: (1) a control interface configured to receive a command to photograph a scene and (2) a best shot determiner, coupled to the control interface and configured to select, after a focused image of the scene has been acquired and in response to receiving the command, a captured image of the scene based on sharpness metrics.

Abstract: A solution is proposed for processing input in a lower power user interface of touch-sensitive display panels. According to an embodiment, a mobile computing device is placed in the low power mode. During this mode, the sensor controller produces a raw event/interrupts on a detected touch. Upon detecting a touch, the sensor controller also automatically increases the scan rate of the touch sensor, while the triggered event or interrupt proceeds to wake the system into a higher power state. Subsequent touch data received while the system is booting into the higher power state is buffered by the timing controller, or by a bridge chipset, while the processor(s) in the power up. When awake, the processor(s) collect the touch samples from the buffer, and processes the touch samples, generating updated displays where necessary.

Abstract: The present invention facilitates efficient and effective encoding and motion detection. A system and method can include: receiving graphics frame information; performing a motion vector analysis including candidate selection utilizing motion vectors that processing has previously been initiated for; and performing an encoding utilizing results of the motion vector analysis. A candidate motion vector is selected based upon balancing of performance and accuracy. The candidate motion vector can be associated with a macro-block that is spatially and temporally close to the left in the same row as the current macro-block. In one exemplary implementation, the candidate motion vector can be within 1 to 8 macro-blocks to the left of the current macro-block. A motion vector candidate selection process for a current macro-block can be performed in which a motion vector associated with another macro-block that has completed motion vector analysis is included as a candidate for the current macro-block.

Abstract: A system includes a processing unit and a memory system coupled to the processing unit. The processing unit is configured to mark a memory access in the series of instructions as a priority memory access as a consequence of the memory access having a dependent instruction following less than a threshold distance after the memory access in the series of instructions. The processing unit is configured to send the marked memory access to the memory system.

Abstract: One aspect of the present disclosure provides an IC substrate, comprising a first material layer located on a first side of the IC substrate, and a second material layer located on a second, opposing side of the IC substrate, wherein the second material layer has a higher coefficient of thermal expansion CTE value than the first material layer.