Abstract: A power management unit for improving power efficiency of an electronic device. The power management unit includes a first and a second stage power regulator and a control circuitry. The first stage power regulator includes a switching regulator to efficiently adjust an input voltage based on a feedback signal. The adjusted input voltage provides the second stage power regulator that includes low dropout voltage regulators with an input voltage close to its output. Thus, power dissipation in the second stage is reduced by reducing the voltage differential between the input and desired output voltages. The second stage turns on/off power to units of the electronic device. The control circuitry generates the feedback signal based on dropout voltages of the low dropout voltages, the desired output voltage and the adjusted input voltage. The largest dropout voltage is selected and adds it to the desired output voltage to generate the feedback signal.

Abstract: One embodiment of the present invention sets forth multigrid generation technique which enables accurate simulations of large scale three dimensional (3D) fluid volumes. A model of the fluid to be simulated is represented using a cell grid. The generated multigrid provides a hierarchy of increasingly coarser representations of the model that are used by a pressure solver. Eulerian simulation techniques require solving a linear system to determine pressure values for each cell within the cell grid. Different levels of the multigrid are then used to compute the pressure values for different regions of the model, maintaining accuracy near the surface of the fluid while simplifying the computations. The accurate pressure values ensure that the simulation produces detailed features of the water movement. Additionally, the multigrid pressure solver may be optimized for execution by a graphics processor.

Abstract: Disclosed are methods, devices, and systems to digitally control a duty cycle of a switching mode power supply. In one embodiment, a method comprises calculating a base duty cycle using a power management unit of a high-speed processing unit, calculating a dynamic offset duty cycle using the power management unit to apply a transfer function to a sampled feedback voltage signal, and adding the base duty cycle to the dynamic offset duty cycle to obtain a duty cycle of the switching mode power supply. A system comprises a switching mode power supply, a power management unit, a voltage sensor, and an analog to digital converter all embedded within a high-speed processing unit, and a pulse-width modulator coupled between the switching mode power supply and the high-speed processing unit to modulate the duty cycle of the switching mode power supply.

Abstract: A system and method are provided for increasing a voltage range associated with a voltage controlled oscillator. A voltage-to-current converter is provided. Additionally, a current controlled oscillator is provided that is in communication with the voltage-to-current converter. Further, at least one circuit component is provided that is in communication with the voltage-to-current converter for increasing a voltage range with which the apparatus operates as a voltage controlled oscillator.

Abstract: A system and method are provided for launching a callable function. A processing system includes a host processor, a graphics processing unit, and a driver for launching a callable function. The driver is adapted to recognize at load time of a program that a first function within the program is a callable function. The driver is further adapted to generate a second function. The second function is adapted to receive arguments and translate the arguments from a calling convention for launching a function into a calling convention for calling a callable function. The second function is further adapted to call the first function using the translated arguments. The driver is also adapted to receive from the host processor or the GPU a procedure call representing a launch of the first function and, in response, launch the second function.

Abstract: An asymmetrically scaling multiple GPU graphics system wherein the multiple GPUs are asymmetric, meaning that their rendering capabilities and/or rendering power is not equal. The asymmetric scaling multiple GPU graphics system includes a plurality of GPUs configured to execute graphics instructions from a computer system. A GPU output multiplexer and a controller unit are coupled to the GPUs. The controller unit is configured to control the GPUs and the output multiplexer such that the GPUs cooperatively execute the graphics instructions from the computer system.

Abstract: A system, method, and computer program product are provided for affixing a post to a substrate pad. In use, a post is affixed to each of one or more pads of a substrate, where each post receives a ball of a package during an assembly process.

Abstract: Systems and methods for automatically switching scene modes of a monitor may comprise processes and corresponding modules for sending a request to a driver to activate hardware modules of a graphics processing unit (GPU) based on a requirement of a launched application program and then recording identifiers of the activated hardware modules on a list. A record of a scene mode associated with one or more activated hardware modules on the list is located within a scene mode profile table and then the corresponding monitor parameters previously associated with the scene mode are read. The monitor is then automatically adjusted according to the monitor parameters read.

Abstract: Disclosed are methods, an apparatus and a system of synchronous media display through automatic profiles across multiple display units. A method of a display driver involves automatically identifying a hardware profile data associated with a plurality of display units, applying a logic function to the hardware profile data to create a set of synchronization display settings when a match of the hardware profile data with a set of synchronization display settings in a hardware profile lookup table is not found, and automatically applying the set of synchronization display settings to simultaneously display a sequence of graphics signals across the plurality of display units. The method may also include automatically designating one display unit from the plurality of display units as a master display unit and setting a synchronization timing based on an automatic designation of the one display unit from the plurality of display units as the master display unit.

Abstract: A system, method, and computer program product are provided for changing a display refresh rate in an active period. In operation, a request is received to change a display refresh rate. Further, in response to the request, the display refresh rate is changed in an active period during which pixels are being written to a display device.

Abstract: An enhanced fuseless fuse structure is provided herein. Additionally, an IC with an enhanced fuseless fuse structure, a data structure that can be used with this structure and a method of manufacturing an IC are disclosed herein. In one embodiment, the IC includes: (1) a fuse wrapper configured to decode fuseless fuse data for controlling the fuses, (2) JTAG registers configured to store fuse register values in designated blocks, wherein the fuse register values and the designated blocks are determined from the fuseless fuse data and (3) options registers configurable by software to store fuse override data for modifying the fuse register values.

Abstract: A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory.

Abstract: A subsystem is configured to apply an offset voltage to a test, or canary, SRAM write driver circuit to create a condition that induces failure of the write operation. The offset voltage is incrementally increased until failure of the test write operation occurs in the canary SRAM circuit. The subsystem then calculates a probability of failure for the actual, non-test SRAM write operation, which is performed by an equivalent driver circuit with zero offset. The subsystem then compares the result to a benchmark acceptable probability figure. If the calculated probability of failure is greater than the benchmark acceptable probability figure, corrective action is initiated. In this manner, actual failures of SRAM write operations are anticipated, and corrective action reduces their occurrence and their impact on system performance.

Abstract: A method of designing a floorplan for an integrated circuit comprises executing one or more automated placement processes on one or more seed floorplans to generate at least one output floorplan for each of the one or more seed floorplans, wherein the one or more automated placement processes are included in a plurality of pre-selected automated placement processes. The method further comprises computing a quality score for each output floorplan and, based on the quality scores, selecting at least one of the output floorplans for further execution via at least one automated placement process included in the plurality of pre-selected automated placement processes.

Abstract: A subsystem configured to write data to a static random access memory cell employs a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the SRAM cell in the gate circuit of the single N-channel MOS device in the drive path. Specifically, the column select signal controls a semiconductor junction that interrupts the data connection to the gate. In this manner, the column select control is removed from the drive path, thus increasing drive strength. Further, a second semiconductor junction connects the gate of the single NMOS device in the drive path when the gate signal is interrupted.

Abstract: A true random number generator, a method of generating a true random number and a system incorporating the generator or the method. In one embodiment, the generator includes: (1) a ring oscillator including inverting gates having power inputs and (2) a time-varying power supply coupled to the power inputs to provide power thereto and including power perturbation circuitry operable to perturb the power provided to at least one of the power inputs.

Abstract: A dynamic multiple input rail switching unit includes a plurality of DC input voltage rails and a rail switching section coupled to the plurality of DC input voltage rails that is configured to individually connect selected ones of the plurality of DC input voltage rails to a switched rail output. The dynamic multiple input rail switching unit also includes a rail selection section that is coupled to the rail switching section and configured to dynamically choose the selected ones by balancing rail supply currents from the plurality of DC input voltage rails based on rail supply current capacity margins and a switched rail output current. A dynamic multiple input rail switching unit operating method, and a dynamic multiple input rail power converter are also provided.

Abstract: Circuits, methods, and apparatus for modifying the data rate of a data bus. In a circuit having two processors coupled by a data bus, the processors each learn that the other is capable of operating at a modified data rate. The data rate is then changed to the modified rate. Each processor may learn of the other's capability by reading a vendor identification, for example from a vendor defined message stored on the other processor. Alternately, each processor may provide an instruction to the other to operate at the modified rate, for example by writing to the other processor's extended capability registers. In another circuit having two processors communicating over a bus, it is determined that both are capable of transmitting and receiving data at a modified data rate. An instruction is provided to one or both of the processors to transmit at the modified rate.

Abstract: One embodiment of the present invention sets forth a system for displaying images including a hardware display controller engine that receives a rendered image. The system also includes an output compositor that composites a first image and the rendered image to create a second composited image. Finally, the system includes a display to display the second composited image.

Abstract: A proximity display system includes a mobile device that is enabled for Miracast sourcing and that provides a screen display. The proximity display system also includes a plurality of display units, which is enabled for Miracast sinking and is also coupled to the mobile device. Additionally, the proximity display system further includes a proximity sensing unit, which is coupled to the plurality of display units and enables a presentation of the screen display on a selected one of the plurality of display units based on a transmission signal strength received from the mobile device at the selected one. A method of operating a proximity display system is also included.