Abstract: Efficient and effective permission confidential information protection systems and methods are described. The secure information protection systems and methods facilitate storage of confidential information in a manner safe from rogue software access. In one embodiment, a confidential information protection method is implemented in hardware and facilitates protection against software and/or Operating System hacks. In one exemplary implementation, a confidential information protection method includes setting a permission sticky bit flag to a default state upon system set up. The permission sticky bit flag access permission indication is adjusted at system reset in accordance with an initial application instruction. Access to the confidential information is restricted in accordance with the permission sticky bit and the permission sticky bit is protected from adjustments attempting to violate the permission indication.

Abstract: One embodiment of the present invention sets forth a technique for assigning a compute task to a first processor included in a plurality of processors. The technique involves analyzing each compute task in a plurality of compute tasks to identify one or more compute tasks that are eligible for assignment to the first processor, where each compute task is listed in a first table and is associated with a priority value and an allocation order that indicates relative time at which the compute task was added to the first table. The technique further involves selecting a first task compute from the identified one or more compute tasks based on at least one of the priority value and the allocation order, and assigning the first compute task to the first processor for execution.

Abstract: In a raster stage of a graphics processor, a method for tile based precision rasterization. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive at a first level precision to generate a plurality of tiles of pixels. The tiles are then rasterized at a second level precision to generate covered pixels. The covered pixels are then output for rendering operations in a subsequent stage of the graphics processor.

Abstract: A circuit and method for filtering adjacent channel interferers. One embodiment of an adjacent channel filtering circuit for reducing adjacent channel interference with an in-band signal, includes: (1) a radio frequency (RF) circuit configured to receive and down-convert an RF signal to a baseband signal containing an in-band signal and adjacent channel components, (2) a controlled single pole filter electrically coupled to the RF circuit and configured to reject the adjacent channel components and cause a predetermined attenuation in the in-band signal, (3) a baseband circuit coupled to the controlled single pole filter and configured to condition the baseband signal for conversion to a digital signal, and (4) a digital circuit coupled to the baseband circuit and configured to receive the digital signal and compensate for the predetermined attenuation.

Abstract: One embodiment of the present invention sets forth a mechanism for transmitting and receiving ground-referenced single-ended signals. A transmitter combines a direct current (DC) to DC converter including a flying capacitor with a 2:1 clocked multiplexer to drive a single-ended signaling line. The transmitter drives a pair of voltages that are symmetric about the ground power supply level. Signaling currents are returned to the ground plane to minimize the generation of noise that is a source of crosstalk between different signaling lines. Noise introduced through the power supply is correlated with the switching rate of the data and may be reduced using an equalizer circuit.

Abstract: A system, method, and computer program product are provided for invalidating cache lines. In use, one or more cache lines that hold data from within a region of a memory address space are invalidated.

Abstract: A method is provided for depicting on a display, an object within a simulated environment having clothing. In this method, the clothing is represented as a series of vertices that include vertices that are attached to the object and vertices that are not attached to the object. The method improves upon position based dynamics algorithm by constraining unattached vertices to be a predefined distance away from attached vertices that are connected thereto to compensate for overstretching in the simulated clothing.

Abstract: One embodiment of the present invention sets forth a technique for providing a unified memory for access by execution threads in a processing system. Several logically separate memories are combined into a single unified memory that includes a single set of shared memory banks, an allocation of space in each bank across the logical memories, a mapping rule that maps the address space of each logical memory to its partition of the shared physical memory, a circuitry including switches and multiplexers that supports the mapping, and an arbitration scheme that allocates access to the banks.

Abstract: A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

Abstract: A system, method, and computer program product for generating high-dynamic range image data is disclosed. The method includes the steps of receiving image sensor data from an interleaved image sensor. The interleaved the image sensor includes a first portion of pixels exposed for a first exposure time and a second portion of pixels exposed for a second exposure time that is shorter than the first exposure time. The method further includes the steps of identifying a first subset of pixels in the second portion having an intensity value above a first threshold value, identifying a second subset of pixels in the first portion having an intensity value below a second threshold value, and generating high-dynamic range (HDR) data based on the first subset and the second subset.

Abstract: A security command protocol provides secure authenticated access to an auxiliary security memory within a SCSI storage device. The auxiliary security memory acts as an authenticated separate secure storage area that stores sensitive data separately from the user data area of the SCSI storage device. The security command protocol is used to access the auxiliary security memory. The security command protocol allows a trusted execution environment to transport sensitive data to and from storage in the auxiliary security memory. The regular execution environment does not have access to the security command protocol or the auxiliary security memory. The security command protocol and auxiliary security memory eliminate the need for additional secure storage components in devices that provide the security features of firmware TPM.

Abstract: A method and a system are provided for performing memory access assist using voltage boost. A memory access request is received at a storage cell array that comprises two or more subarrays, each subarray including at least one row of storage cells. The voltage boost is applied, during the memory access, to a first negative supply voltage of a first storage cell subarray of the two or more storage cell subarrays. The first negative supply voltage of the first storage cell subarray is lower than a second negative supply voltage of a second storage cell subarray of the two or more storage cell subarrays.

Abstract: A system, method, and computer program product are provided for implementing a pinlight see-through near-eye display. Light cones configured to substantially fill a field-of-view corresponding to a pupil are generated by an array of pinlights positioned between a near focus plane and the pupil. Overlap regions where two of more light cones intersect at a display layer positioned between the array of pinlights and the pupil are determined. The two or more light cones are modulated based on the overlap regions to produce a target image at or beyond the near focus plane.

Abstract: A radio frequency (RF) circuit for intra-band and inter-band carrier aggregation includes a receive path configured to receive an input signal. The RF circuit includes a low noise amplifier which has multiple separate input stages and multiple separate output stages. Each input stage has multiple separate input paths, wherein each separate input path is configured to be separately activated and connected to one of the output stages. Each separate output stage is configured to be separately activated and connected to a signal mixer that provides signal demodulation of the input signal employing aggregation of carriers corresponding to intra-band or inter-band signals. Methods of operating the RF circuit for intra-band and inter-band carrier aggregation are also provided.

Abstract: A system, method, and computer program product are provided for allocating processor resources to process compute workloads and graphics workloads substantially simultaneously. The method includes the steps of allocating a plurality of processing units to process tasks associated with a graphics pipeline, receiving a request to allocate at least one processing unit in the plurality of processing units to process tasks associated with a compute pipeline, and reallocating the at least one processing unit to process tasks associated with the compute pipeline.

Abstract: Various embodiments relating to reducing memory bandwidth consumed by a continuous scan display screen are provided. In one embodiment, scoring criteria are applied to a reference image of a first image format having a first bit depth to generate an image conversion score. The scoring criteria are based on a histogram of one or more characteristics of the reference image. If the image conversion score is greater than a threshold value, then the reference image is converted to a modified image of a second image format having a second bit depth less than the first bit depth, and the modified image is scanned onto the continuous scan display screen. If the image conversion score is less than the threshold value, then the reference image is scanned onto the continuous scan display screen.

Abstract: A system, method, and computer program product are provided for subdividing a quadratic Bezier curve. The method includes the steps of receiving a quadratic Bezier curve defined by a plurality of control points including at least a first endpoint and a second endpoint. The quadratic Bezier curve is uniformly subdivided based on an angle between a first tangent at the first endpoint and a second tangent at the second endpoint to produce a piecewise representation of the quadratic Bezier curve including two or more Bezier curve segments.

Abstract: A system, method, and computer program product are provided for calculating shader program intermediate values. The method includes the steps of receiving a graphics primitive for processing according to a shader program including a first set of instructions and a second set of instructions, executing the first set of instructions by a processing pipeline to calculate multi-pixel intermediate values, executing the second set of instructions by the processing pipeline to calculate per-pixel values based on at least the multi-pixel intermediate values, and repeating the receiving and executing of the first and second sets of instructions for one or more additional graphics primitives.

Abstract: A system, method, and computer program product are provided for remapping registers based on a change in execution mode. A sequence of instructions is received for execution by a processor and a change in an execution mode from a first execution mode to a second execution mode within the sequence of instructions is identified, where a first register mapping is associated with the first execution mode and a second register mapping is associated with the second execution mode. Data stored in a set of registers within a processor is reorganized based on the first register mapping and the second register mapping in response to the change in the execution mode.

Abstract: Techniques for handling an interrupt in the rasterizer, in accordance with embodiment of the present technology, start with rasterizing one or more primitives of a first context. If an interrupt is received, the tile count of tiles of a current primitive that have been coarse rasterized is saved in a backing store. After storing the tile count, the one or more primitives of a second context are rasterized. After the second context is served, the coarse rasterization of the current primitive of the previous context is rerun without output until the tile corresponding to the stored tile count is coarse rasterized. Thereafter, rasterization of the current primitive of the first context from the next tile beyond the stored tile count is continued until rasterization is completed or another interrupt is received and the above described process is repeated.