Patents Assigned to NVidia
  • Patent number: 9064061
    Abstract: A method and system are implemented to instantaneously detect a hot plugging of a video connector in a computer device by detecting a change in the electrical state of one ground pin of the video connector. The computer device comprises a video connector having at least two ground pins, a processing unit, and a hot-plugging detection circuit coupled between the processing unit and one of the ground pins of the video connector, wherein the hot-plugging detection circuit is configured to detect a hot plugging of the video connector based on a change in voltage potential of the ground pin.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: June 23, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Shany-I Chan, Yu-Kuo Chiang, Shih-Da Wu, Patrick Beaulieu, William S. Herz, Li-Ling Chou, Ching-Yee Feng
  • Patent number: 9066337
    Abstract: A wireless subscriber communication unit is provided for operation in a cellular communication system having a plurality of shared uplink and downlink transmission resources, each divided into sets of mutually exclusive resources. The shared uplink transmission resources are defined in terms of codes and timeslots. The communication unit comprises a receiver, control, and transmitter unit. The receiver unit receives scheduling information including an assignment of a scheduled uplink transmission resource from the shared uplink transmission resources from a network infrastructure apparatus. The control unit derives an uplink resource identifier related to the scheduled uplink transmission resource from the received scheduling information. The transmitter unit transmits an uplink transmission, which includes the uplink resource identifier, using the scheduled uplink transmission resource.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: June 23, 2015
    Assignee: NVIDIA CORPORATION
    Inventor: Nicholas William Anderson
  • Patent number: 9066285
    Abstract: A modem comprising: a wireless transceiver for connecting to a wireless cellular network; second interface apparatus for connecting to a terminal; and processing apparatus which performs operations of a wireless cellular modem to enable the terminal to access a further, packet-based network via access points of the wireless cellular network. The processing apparatus receives a modem command from the terminal, the modem command comprising a field for specifying the name of one of the access points in the form of a text string. The field comprises the names a plurality of the access points and one or more separator characters between them. The processing apparatus is configured to extract each of the names from the field based on the one or more separator characters, and to establish a different respective channel with each of the plurality of access points based on the extracted names.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: June 23, 2015
    Assignee: Nvidia Corporation
    Inventors: Bruno De Smet, Flavien Delorme
  • Patent number: 9064314
    Abstract: A MacBeth color checker chart automatic detection system includes an imaging unit that provides an image and a processing unit that applies an edge detection operation to the image and performs a flood-fill operation on the image to provide a flood-filled image. Additionally, the MacBeth color checker chart automatic detection system includes a testing unit that tests the flood-filled image to provide a modified flood-fill image, wherein a set of heuristic tests are employed to automatically determine quantity and location of MacBeth color checker charts. Generally, the set of heuristic tests are employed to automatically reject regions that are unlikely to belong to a MacBeth color checker chart and to cluster the remaining regions that are likely to belong to a Macbeth color checker chart. A MacBeth color checker chart automatic detection method is also provided.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: June 23, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Goran Devic, Shalini Gupta
  • Patent number: 9064322
    Abstract: One embodiment of the present invention sets forth a method for accessing display configuration information in a multi-graphics-processing-unit (multi-GPU) system, which includes the steps of asserting a select signal to steer the display configuration information of a display device, which is coupled to a discrete GPU (dGPU), to a motherboard GPU (mGPU) in the multi-GPU system if dGPU is unavailable, and validating the display configuration information prior to availing the dGPU or the display device as an option to be selected.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: June 23, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: David Wyatt, Ludger Mimberg
  • Publication number: 20150169289
    Abstract: A system and method are provided for performing 32-bit or dual 16-bit floating-point arithmetic operations using logic circuitry. An operating mode that specifies an operating mode for a multiplication operation is received, where the operating mode is one of a 32-bit floating-point mode and a dual 16-bit floating-point mode. Based on the operating mode, nine recoding terms for a mantissa of at least one floating-point input operand are determined. A dual-mode multiplier array circuit that is configurable to generate partial products for either one 32-bit floating-point result or for two 16-bit floating-point results computes the partial products based on the nine recoding terms. The partial products are processed to generate an output based on the operating mode.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: NVIDIA Corporation
    Inventors: David C. Tannenbaum, Srinivasan Iyer
  • Publication number: 20150169101
    Abstract: Embodiments of the present invention can be configured to recognize and/or track certain types of touch input detected by a touch sensor, such as stylus input, during the performance of standard “full” touch scans in which each drive line of the touch sensor is generally scanned. Upon detection of these input types, “partial” touch scan operations can advantageously be performed which can dynamically reduce the number of lines scanned in a power-saving manner. These partial scans can be configured to intelligently initially scan the area where these input types were last detected so that there is minimal need to return to a previous “full” scan mode. If these specified touch inputs types are not detected during a “partial” scan mode, the touch sensor can be restored to a “full” scan mode until a subsequent detection of the touch input is determined, in which the touch sensor can be returned to a “partial” scan mode. Each time a partial scan is used, power is saved.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 18, 2015
    Applicant: Nvidia Corporation
    Inventor: David JUNG
  • Publication number: 20150171631
    Abstract: A system, method, and computer program product are provided for merging two or more supply rails into a merged supply rail. The method comprises receiving two or more current measurement signals associated with two or more supply rails, selecting one supply rail from the two or more supply rails, based on the current measurement signals, and enabling the selected supply rail to source current into a merged supply rail.
    Type: Application
    Filed: December 18, 2013
    Publication date: June 18, 2015
    Applicant: NVIDIA Corporation
    Inventors: Samuel Richard Duell, Gabriele Gorla, Yaoshun Jia, Qi Lin, Andrew Bell
  • Publication number: 20150170408
    Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Yong HE, Eric B. LUM, Eric ENDERTON, Henry Packard MORETON, Kayvon FATAHALIAN
  • Publication number: 20150170409
    Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Yong HE, Eric B. LUM, Eric ENDERTON, Henry Packard MORETON, Kayvon FATAHALIAN
  • Patent number: 9058677
    Abstract: One embodiment of the present invention sets forth a technique for efficiently performing broad phase collision detection using parallel spatial subdivision. The technique involves organizing candidate objects according to a hashed representation of each object centroid, constructing a cell identification (ID) array, sorting the cell ID array, creating a collision cell list, and traversing the collision cell list. The result is a candidate list of object groups that may collide, based on an initial assessment of spatial proximity. Whether a given pair of objects actually collides is determined by a precise narrow phase collision analysis.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: June 16, 2015
    Assignee: NVIDIA CORPORATION
    Inventor: Scott M. Le Grand
  • Patent number: 9058672
    Abstract: One embodiment of the present invention sets forth a technique controlling the pixel location at which the plane equation is evaluated. Multiple pixel offsets (dx, dy) may be specified that each define to a sub-pixel sample position. Attributes are then calculated for each sub-pixel sample position that is covered by a geometric primitive. One advantage of the technique is that anti-aliasing quality may be improved since high frequency color components may be selectively supersampled for particular geometric primitives.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: June 16, 2015
    Assignee: NVIDIA Corporation
    Inventors: John Erik Lindholm, Henry Packard Moreton, Ming Y. Siu, Stuart F. Oberman
  • Patent number: 9058792
    Abstract: Sequential write operations to a unit of compressed memory, known as a compression tile, are examined to see if the same compression tile is being written. If the same compression tile is being written, the sequential write operations are coalesced into a single write operation and the entire compression tile is overwritten with the new data. Coalescing multiple write operations into a single write operation improves performance, because it avoids the read-modify-write operations that would otherwise be needed.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: June 16, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: John H. Edmondson, Robert A. Alfieri, Michael F. Harris, Steven E. Molnar
  • Patent number: 9058678
    Abstract: One embodiment of the present invention sets forth a technique for efficiently performing broad phase collision detection using parallel spatial subdivision. The technique involves organizing candidate objects according to a hashed representation of each object centroid, constructing a cell identification (ID) array, sorting the cell ID array, creating a collision cell list, and traversing the collision cell list. The result is a candidate list of object groups that may collide, based on an initial assessment of spatial proximity. Whether a given pair of objects actually collides is determined by a precise narrow phase collision analysis.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: June 16, 2015
    Assignee: NVIDIA CORPORATION
    Inventor: Scott M. Le Grand
  • Patent number: 9058453
    Abstract: A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: June 16, 2015
    Assignee: NVIDIA Corporation
    Inventors: Stephen William Keckler, William J. Dally, Steven Lee Scott, Brucek Kurdo Khailany, Michael Allen Parker
  • Patent number: 9060355
    Abstract: A method of handling messages at a user equipment received from a communications network during a procedure, the method implemented at the user equipment comprising: receiving a first message from the network while the user equipment is in a first operating state; processing the first message and entering a second operating state in response to receiving the first message; receiving a second message from the network while the user equipment is in the second operating state; detecting that the second message is a duplicate of the first message; and checking for an indication that the second message is a potential duplicate of the first message. If the indication is not present, the method further comprises transmitting a failure notification to the network. If the indication is present, the method further comprises discarding the second message and not transmitting a failure notification to the network to prevent failure of the procedure.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: June 16, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Tim Rogers, Alexander May-Weymann
  • Patent number: 9059054
    Abstract: One aspect of the present disclosure provides an IC substrate, comprising a first material layer located on a first side of the IC substrate, and a second material layer located on a second, opposing side of the IC substrate, wherein the second material layer has a higher coefficient of thermal expansion CTE value than the first material layer.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: June 16, 2015
    Assignee: Nvidia Corporation
    Inventor: Leilei Zhang
  • Publication number: 20150163324
    Abstract: A request management subsystem is configured to establish service classes for clients that issue requests for a shared resource on a computer system. The subsystem also is configured to determine the state of the system with respect to bandwidth, current latency, frequency and voltage levels, among other characteristics. Further, the subsystem is configured to evaluate the requirements of each client with respect to latency sensitivity and required bandwidth, among other characteristics. Finally, the subsystem is configured to schedule access to shared resources, based on the priority class of each client, the demands of the application, and the state of the system. With this approach, the subsystem may enable all clients to perform optimally or, alternatively, may cause all clients to experience an equal reduction in performance.
    Type: Application
    Filed: December 9, 2013
    Publication date: June 11, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Evgeny BOLOTIN, Zvika GUZ, Adwait JOG, Stephen William KECKLER, Michael Allen PARKER
  • Publication number: 20150160911
    Abstract: A method includes providing a memory unit in a computing device already including a number of processors communicatively coupled to a memory through a system bus, and providing a non-system bus based dedicated channel between the number of processors and the memory unit. The method also includes rendering a different video frame and/or a surface on each processor of the number of processors, and leveraging the memory unit to store a video frame and/or a surface rendered on a processor therein through the non-system bus based dedicated channel. Further, the method includes copying, to other processors, the stored video frame and/or the surface rendered on the processor from the memory unit through the non-system bus based dedicated channel, and scanning out, through the number of processors, the video frame and/or the surface rendered on the processor following the copying to enable display thereof on a corresponding number of displays.
    Type: Application
    Filed: December 10, 2013
    Publication date: June 11, 2015
    Applicant: NVIDIA Corporation
    Inventors: Praful Jotshi, Arpit Agrawal
  • Publication number: 20150161810
    Abstract: Systems and methods for providing a mechanism of simulating fluid dynamics while maintaining the incompressibility of a fluid based on a position based dynamics (PBD) framework. A set of constraint equations that enforce constant density of the particles in a fluid object are formulated in terms of neighbor particle positions. The formulated constraint equations can be solved iteratively in a Jacobi method to obtain a new position and new velocity of each particle in large time steps. Voracity confinement may be introduced to simulate turbulent motions of the fluid object based on an unnormalized curl of the particle velocities. A positive artificial pressure term can be incorporated in particle position updates to reduce particle clustering or clumping effect caused by negative pressures related to neighbor deficiencies.
    Type: Application
    Filed: December 10, 2013
    Publication date: June 11, 2015
    Applicant: NVIDIA Corporation
    Inventors: Miles MACKLIN, Matthias MULLER