Abstract: A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.

Abstract: A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.

Abstract: A sensor node is provided having a radio frequency (RF) circuit and a sensor interface circuit. The RF circuit wirelessly harvests energy from an external device such as a smart phone to produce a voltage at an output to charge a storage capacitor. The sensor interface circuit is configured to communicate with a sensor. In response to a request from the external device, the sensor node provides a voltage level of the capacitive element to the external device. The external device uses the voltage level to determine capabilities of the sensor node and to control sensing functions of the sensor node. In another embodiment, a method is provided to operate the sensor node.

Abstract: A communication system includes a digital data processor that produces a digital data sample and one or more control bits. A serialized transmit interface assembles the digital data sample and the control bit(s) into first and second data packets of a data frame, and sends the data frame over a signal line. A serialized receive interface receives the data frame and produces a reconstructed digital data sample and the control bit(s) from the first and second data packets. A control circuit coupled to the serialized receive interface produces a control signal from the control bit(s). The communication system may include a converter circuit, which produces an RF input signal by performing a digital-to-analog conversion of the reconstructed digital data sample, and by upconverting the resulting analog data sample signal to RF. A power amplifier amplifies the RF input signal and modifies operation of a sub-circuit based on the control signal.

Abstract: Aspects of the subject disclosure may include, for example, detecting placement of a receiver coil of a device upon a transmitter coil of a wireless charger, identifying a transmitter coil type of the transmitter coil, identifying a receiving coil type associated with the receiver coil of the device, comparing the transmitter coil type to the receiver coil type, generating a message to move the device to a different position of the wireless charger responsive to detecting a mismatch between the receiving coil type of the device and the transmitting coil type of the wireless charger. Other embodiments are disclosed.

Abstract: A power combiner/splitter for multiple input multiple output (MIMO) applications and a method of making the same. A metallisation stack has a plurality of layers including patterned metal features forming first and second branched arrangements of the power combiner/splitter. Each branched arrangement includes a port located at one end of that branched arrangement, and a plurality of further ports. Each branched arrangement also includes a plurality of bifurcated branches extending between each end of that branched arrangement for dividing/combining a signal passing through that branched arrangement between the port and the plurality of further ports. The metallisation stack further includes a common ground plane that is shared by the first and second branched arrangements. At least some of the patterned metal features forming the first branched arrangement overlie at least some of the patterned metal features forming the second branched arrangement.

Abstract: A system includes an ADC configured to generate a superposition signal by the ADC being configured to under-sample an input signal at a sampling frequency in which the input signal that is input to the analog to digital converter has a bandwidth and the sampling frequency is less than a Nyquist rate for the bandwidth of the input signal. The system includes a digital signal processor (DSP) configured to digitally process the superposition signal to separate the superposition signal into a plurality of bitstreams, where each of the plurality of bitstreams corresponds to information in a different one of a plurality of separable, distinct frequency bands within the input signal. The information in the superposition signal for at least one of the said plurality of bitstreams is present in the input signal at frequencies greater than the sampling frequency, and the DSP is configured to output said plurality of bitstreams.

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form first remnant silicon germanium nanosheet layers (12, 14) in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG1) and to form second remnant silicon germanium nanosheet layers (18, 20) in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG2) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.

Abstract: A method and apparatus are provided in which receiver circuitry and signal processing circuitry may reside. The receiver circuitry receives a FMCW radar signal having a content signal (e.g., a random or information signal) embedded into a radar waveform and indicating a relationship in the FMCW radar signal between beat frequency and time delay. The signal processing circuitry may apply a filter (e.g., filtering with a group delay that approximates or relates to the relationship) that causes a residual error in, due to dispersion of, the content signal, and may account for (e.g., mitigate) the residual error by introduction of a dispersion-related function in further processing of the content signal.

Abstract: A compact planar balun formed on a substrate including a hairpin-shaped conductive microstrip and a single-ended contact. The hairpin-shaped conductive microstrip includes first and second linear segments integrally formed with a U-shaped segment, and a single-ended contact is conductively coupled at a location along the first linear segment. The first and second linear segments each have a first characteristic impedance and are in parallel with each other having a first end forming first and second differential contacts and having a second end. The U-shaped segment has a second characteristic impedance that is less than the first characteristic impedance in order to achieve proper scatter parameter alignment. The U-shaped segment may be generally formed thicker or wider than the linear segments to achieve a reduced characteristic impedance. In the alternative or in addition, co-planer ground metal is formed closer to the U-shaped segment to achieve a reduced characteristic impedance.

Abstract: Various embodiments relate to a method for estimating a breathing rate, including: receiving a plurality of channel state information (CSI) from a wireless device; selecting an initial reference CSI from the plurality of CSI; computing a perturbation index using the initial reference CSI and a portion of the plurality of CSI; determining an optimal reference CSI based upon the perturbation index; re-computing the perturbation index using the optimal reference CSI on a portion of the plurality of CSI subsequent to the optimal reference CSI; and determining a breathing rate from the perturbation index using a frequency analysis of the perturbation index.

Abstract: A signal processor and method of signal processing for a radio receiver is described. An input signal is received together with a spectral repetition interval value of an interferer signal. An interference reference signal is generated from the received spectral repetition interval value and the received signal. The received signal is adapted using the generated interference reference signal.

Abstract: An infrastructure-controller (206) for an infrastructure (202), wherein the infrastructure has a plurality of Bluetooth Low Energy, “BLE”, nodes (208, 210, 212) associated with it. The infrastructure-controller (206) is configured to: identify one of the plurality of BLE nodes as a current-BLE-node (212), and activate the current-BLE-node (212) for communication with a key (204) using BLE signals; determine a communication-quality-indicator for each of the plurality of BLE nodes (208, 210, 212), that represents the quality of communication with the key (204); based on the communication-quality-indicators, identify one of the plurality of BLE nodes as a next-BLE-node (210); and provide connection-information to the next-BLE-node (210) using out-of-band signalling (214). The infrastructure-controller (206) can then deactivate the current-BLE-node (212); and activate the next-BLE-node (212) for continued communication with the key (204) using BLE signals.

Abstract: A power management system includes a capacitor, control logic configured to determine a wait time in response to a comparison of a voltage of the capacitor to a threshold voltage and to initiate a startup upon expiration of the wait time, and a control circuit configured to charge the capacitor, discharge the capacitor, and provide the voltage of the capacitor to the control logic.

Abstract: An array of bit cells is programmed with user data, each row including a corresponding word line and each column including a corresponding column line. The array includes a plurality of differential PUF bits, each having a first and second bit cell programmed with user data. A first set of sense-amplifiers outputs a set of data bits of the user data, and a second set of sense-amplifiers outputs a set of differential bits, each differential bit based on a differential current between two columns lines of the selected column lines corresponding to the first and second bit cells of a corresponding differential PUF bit along the selected word line. A potential PUF bit generator outputs a set of potential PUF bits based on the set of data bits of the user data from the first set of sense-amplifiers and the set of differential bits from the second set of sense-amplifiers.

Abstract: A processor includes a register file having a plurality of register file addresses, a processing unit, configured to perform processing in accordance with a configuration defined by information stored in the register file, and an instruction sequencer. The instruction sequencer is configured to control the processing unit by retrieving a sequence of instructions from a memory, in which each instruction includes an opcode, and a subset of the instructions includes a data portion. For each instruction in the sequence of instructions, the instruction sequencer performs an action defined by the opcode. The action for the subset of the opcodes includes writing the data portion to a register file address defined by the opcode. The sequence of instructions includes variable length instructions.

Abstract: An adaptive prefetcher for a shared system cache of a processing system including multiple requestors having a cache miss monitor and a prefetch controller. The cache miss monitor monitors requests for information from memory and identifies one of the requestors for which an identified cache line is requested. The prefetch controller submits an adaptive request for a subsequent cache line. The subsequent cache line may be determined based on a latency comparison between a loop latency (LL) of the prefetch controller and a stream latency (SL) of the identified requestor. A latency memory may be included that stores stream latencies for the requestors. The latency comparison may be used to determine how many cache lines to skip relative to the identified cache line, such as according to SL*SK<LL?SL*(SK+1) in which SK is the number of cache lines to skip.

Abstract: A packaged die including a first and a second power supply pad configured to provide a first and a second power supply voltage, respectively, and circuitry powered by the first power supply voltage. A power pad handling circuitry includes a selectively enablable pull-down path coupled between the first power supply pad and the second power supply pad, a storage circuit configured to store a pull-down path enable bit, a clock input coupled to receive a boot clock, and an asynchronous input coupled to receive a power-on-reset (POR) signal. In response to assertion of the POR signal, the pull-down pat is enabled regardless of any signal received at the clock input and regardless the value of the pull-down path enable bit. When reset has completed, a value of the pull-down path enable bit is provided upon an active edge of the boot clock to selectively enable the pull-down path.

Abstract: A radar system, apparatus, architecture, and method are provided with a transmitter that produces a plurality of distinct FanTOM signals that are transmitted as N RF-encoded transmit signals in an overlapped fashion such that the pulse repetition interval and frame length are kept short; a receiver that processes target return signals reflected from the N RF-encoded transmit signals with a mixer to produce an IF signal which is filtered with one or more notch filters clocked with a sampling clock frequency to control harmonic notch frequencies to suppress transmitter spill-over and close-in self-clutter interference, thereby producing a filtered IF signal that is converted to a digital signal with an analog-to-digital converter that is clocked with the sampling clock frequency; and a radar processor that processes the digital signal to generate a range spectrum comprising N segments that correspond, respectively, to the N RF-encoded transmit signals.

Abstract: Aspects of the subject disclosure may include, for example, remapping a first address bus into a first remapped address bus by replacing bit lines of the first address bus with attribute bit lines, the first remapped address bus supplying updated address information, connecting the first address remapped bus to an address translation unit (ATU), the ATU configured to translate the updated address information into translated address information supplied to a second address bus, and remapping the second address bus into a second remapped address bus by replacing a portion of the second address bus with the bit lines of the first address bus that were replaced by the attribute bit lines, the second remapped address bus changing the translated address information into updated translated address information.