Abstract: The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analog signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analog signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.

Abstract: According to a first aspect of the present disclosure, an electronic tamper detection device is provided, comprising a tamper loop and a deformable component, wherein a deformation of said component indicates that the tamper loop has been broken. According to a second aspect of the present disclosure, a corresponding method of producing a tamper detection device is conceived.

Abstract: In an embodiment, a method for analyzing signals from a pixelated capacitive sensor is disclosed. The method involves classifying capacitance signals from sensor cells of a pixelated capacitive sensor into at least one class based on capacitance values for sensor cells indicated by corresponding capacitance signals and assigning an attribute to sensor cells based on the classification of the corresponding capacitance signals.

Abstract: A method, apparatus, article of manufacture, and system are provided for detecting hardware faults on a multi-core integrated circuit device by executing runtime software-based self-test code concurrently on multiple processor cores to generate a first set of self-test results from a first processor core and a second set of self-test results from a second processor core; performing mutual inter-core checking of the self-test results by using the first processor core to check the second set of self-test results from the second processor core while simultaneously using the second processor core to check the first set of self-test results from the first processor core; and then using the second processor core to immediately execute a recovery mechanism for the first processor core if comparison of the first set of self-test results against reference test results indicates there is a hardware failure at the first processor core.

Abstract: Embodiments of ripple generation devices for a constant on-time voltage regulator and methods for ripple generation for a constant on-time voltage regulator are described. In one embodiment, a ripple generation device for a constant on-time voltage regulator includes a ripple generator configured to generate a ripple signal, a detector operably connected to the ripple generator and configured to detect a difference between an amplitude of the ripple signal and at least one reference amplitude and a feedback controller operably connected to the ripple generator and the detector and configured to generate a control signal for controlling the amplitude of the ripple signal based on the detected difference. Other embodiments are also described.

Abstract: Semiconductor device and methods for making the devices includes a buried layer of a first conductivity in a substrate in which a distance between two adjacent ends can be selected to achieve a desired breakdown voltage. A deep well having a first doping concentration of a second conductivity type is implanted in an epitaxial layer above the two adjacent ends of the buried layer. A patterned doped region is formed in the deep well and extending into the epitaxial layer above and separated a distance from the two adjacent ends of the buried lay. The patterned doped region has a second doping concentration of the second conductivity type that is greater than the first doping concentration.

Abstract: An electronic device includes a first memory subsystem, a second memory subsystem and a direct memory access controller. In response to a first type of request from a processor, the direct memory access controller requests data from the first memory subsystem and provides the data to the second memory subsystem. In response to a second type of request from a processor, the direct memory access controller requests an uncompressed matrix from the first memory subsystem, compresses the uncompressed matrix to generate a compressed matrix, and provides the compressed matrix to the second memory subsystem. In response to a third type of request from a processor, the direct memory access controller requests a compressed matrix from the second memory subsystem, un-compresses the compressed matric to generate an uncompressed matrix, and provides the un-compressed matrix to the first memory subsystem.

Abstract: A method of manufacturing a device with six-sided protected walls is disclosed. The method includes fabricating the plurality of devices on a wafer, forming a plurality of contact pads on each of the plurality of devices, cutting a first trench around each of the plurality of devices from a backside of the wafer with an active side having a plurality of contact pads facing down, applying a protective coating on the backside of the wafer thus filling the first trench with a protective material of the protective coating on the backside and cutting a second trench from the active side.

Abstract: A device includes an output circuit that includes an input port at which a signal is received, an output port at which an impedance-adjusted representation of the signal is provided, and a set of bond wires connecting the input and output ports. The device further includes first and second couplers, each including a respective coupling bond wire along the set of bond wires for inductive coupling with the set of bond wires. The first coupler is oriented relative to the distributed-element output circuit to measure forward power provided by the impedance-adjusted representation of the signal via the output port. The second coupler is oriented relative to the output circuit to measure reflected power received via the output port.

Abstract: Various embodiments relate to a method and circuit for combining channels, the method including receiving, by a matching and smoothing filter, a signal from an analog to digital converter and extracting a root mean square signal level, receiving, by a noise power detector (“NPD”), the signal from the ADC and assessing noise contribution on the signal and receiving, by a maximum ratio combiner, the signal from the matching and smoothing filter wherein a combiner selects between using a geometric sum and an arithmetic sum to combine the channels.

Abstract: A method of performing a cryptographic operation using a cryptographic implementation in a cryptographic system, including: receiving, by the cryptographic system, an identifying string value; receiving, by the cryptographic system, an input message; performing, by the cryptographic system, a keyed cryptographic operation mapping the input message into an output message wherein the output message is the correct result when the identifying string value is one of a set of binding string values, wherein the set includes a plurality of binding string values.

Abstract: There is disclosed an NFC device comprising an NFC communication unit and a memory unit; the NFC device being arranged to receive, through the NFC communication unit, a device identifier of a computing device and to store said device identifier in the memory unit; the NFC device further being arranged to send, upon or after storing said device identifier, at least one software installation key through the NFC communication unit to the computing device. Furthermore, a corresponding software installation method, software uninstallation method, computer program and article of manufacture are disclosed.

Abstract: A memory includes a first memory cell; and a second memory cell. A selectable current path is coupled between the first memory cell and the second memory cell. The selectable current path includes a first transistor. A first amplifier is coupled in a first feedback arrangement between the first memory cell and the first transistor. During a read operation of the first memory cell, a current through the first memory cell is substantially equal to a current through the second memory cell. The memory cell may include a magnetic tunnel junction (MTJ).

Abstract: A method for computing the distance between two encrypted data vectors using elliptic curve cryptography.

Abstract: There is described a method of managing a flow of data packets in a multiple-processing entity system comprising a plurality of look-up tables adapted to store information associated to actions to be performed on packets received by the system. The method comprises storing, on a per entry basis, in a shadowed entry associated to any table entry being updated, the previous content of said table entry being updated, in association with a table entry version number, for use for managing packets received in the system prior to any update operation. It is thus possible to continue using look-up tables while updating process is being carried out for some or all of the table entries. The solution provides benefits for systems that are limited in space and cost, by use of minimal memory thanks to the storing of small shadowed data instead of full shadowed table.

Abstract: A switch mode power supply can include a bipolar device (e.g., bipolar junction transistor) connected in series with a capacitor and operable as a bipolar clamp switch where the bipolar device can be turned on by forward biasing a collector-base junction. The capacitor connected in association with the bipolar device can keep the bipolar clamp switch conductive for a limited time based on energy obtained from a transformer primary winding and stored in the capacitor when the base-collector junction bias is reversed. Storage charge properties of the bipolar clamp switch can be used to keep it conductive and working as an active clamp without requiring a high driver circuit.

Abstract: A processing device includes an instruction memory to store executable applications that are executable by a target processor, and a compiler. The compiler includes a builder module and a call graph generator. The builder module to build executable applications for the target processor based on a set of instructions. The call graph generator to create a first call graph that indicates a stack usage for each call path of the executable applications. If a first executable application built by the builder module includes a call path that exceeds a stack size constraint of the target processor, the builder module to optimize only functions within the call path that exceeds the stack size constraint in response to the request from the evaluation monitor, and to build a second executable application based on the set of instructions. The second executable application is optimized for stack memory usage of the target processor.

Abstract: A system is provided that includes a mechanical resonator, and an analog circuit coupled to the mechanical resonator. The analog circuit is arranged to receive a mechanical resonator measurement signal having a quadrature error from the mechanical resonator, and to extract a quadrature error signal from the mechanical resonator measurement signal using a quadrature clock. A digital quadrature controller is coupled to the analog circuit and is arranged to generate a quadrature error compensation signal from the extracted quadrature error signal and apply the quadrature error compensation signal to the mechanical resonator or the mechanical resonator measurement signal to reduce quadrature error in the mechanical resonator measurement signal error.

Abstract: An integrated circuit for a packaged device is proposed. The circuit comprises: a circuit having first and second electromagnetic radiating elements fabricated on a die; a package substrate comprising an upper surface and a lower surface; and a grounding layer provided on the lower surface of the package substrate, the grounding layer being adapted to connect to a grounding plane of a printed circuit board. The die is mounted on the upper surface of the package substrate. The grounding layer comprises a void, at least a portion of the void being positioned so as to at least partially electromagnetically isolate the first electromagnetic radiating element from the second electromagnetic radiating element.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a channel, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.