Abstract: An all digital phase locked loop system for tracking a variable frequency input signal and method of operation are described. The ADPLL system includes a digital phase locked loop, including a digitally controlled oscillator, and a model of the digitally controller oscillator. The model represents the behaviour of the digitally controlled oscillator as a function of frequency and has a model input arranged to receive a signal indicating a current target frequency. The model is configured to output at least one control signal to control the frequency of the digitally controlled oscillator to be closer to the current target frequency. The digital phase locked loop is configured to control the digitally controlled oscillator to reduce any difference between the frequency of the digitally controlled oscillator and the current target frequency arising from any deviation of the model of the digitally controlled oscillator from the digitally controlled oscillator.

Abstract: An antenna for transmitting a first frequency and a second frequency signals is enclosed. The antenna includes a first metallic section having a first end and a second end, a second metallic section located on a side of the first metallic section and having a first end and a second end. The second metallic section is separated from the first metallic section by a first non-conducting gap. The antenna further includes a third metallic section located on a side of the second metallic section and having a first end and a second end. The third metallic section is separated from the second metallic section by a second non-conducting gap. The first end of the first metallic section is connected to a first electronic circuit, the first end of the third metallic section is connected to a second electronic circuit, and the first end of the second metallic section is connected to a feeding port. The second end of the first metallic section is electrically attached to a first metallic plate.

Abstract: A charge pump driver circuit (320) arranged to output a charge pump control signal (325). The charge pump driver circuit (320) includes a bias current source component (330) arranged to generate a bias current (335), a control stage (340) and an output stage (350). The control stage (340) is coupled to the bias current source component (330) and arranged to receive the bias current (335). The control stage (340) is further arranged to receive an input signal (215) and to generate a control current signal (345) proportional to the bias current (335) in accordance with the input signal (215). The output stage (350) is arranged to receive the control current signal (345) generated by the control stage (340) and to generate the charge pump control voltage signal (325) based on the control current signal (345) generated by the control stage (340). The bias current source component (330) is arranged to vary the bias current (335) in response to variations in temperature.

Abstract: Embodiments of a packaged semiconductor device are provided, which includes a flag of a lead frame having a top surface and a bottom surface; a redistribution layer (RDL) structure formed on the top surface of the flag, the RDL structure including a first connection path having a first exposed bonding surface in a top surface of the RDL structure; and a first wirebond connected to the first exposed bonding surface and to a lead of the lead frame.

Abstract: An interference sensor device is disclosed. The interference sensor device includes a first conductive plate, a second conductive plate aligned parallel to the first conductive plate, a non-conductive matter between the first conductive plate and the second conductive plate and a coil electrically coupled to the first conductive plate and the second conductive plate.

Abstract: Embodiments of methods and systems for operating a communications device that communicates via inductive coupling are described. In an embodiment, a method for operating a communications device that communicates via inductive coupling involves detecting a system condition associated with the communications device and tuning a matching network of the communications device in response to the system condition, where the matching network includes a hybrid transformer that separates a receiver of the communications device from a transmitter of the communications device. Other embodiments are also described.

Abstract: A Doherty amplifier module includes first and second amplifier die. The first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal. The second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal. A phase shift and impedance inversion element is coupled between the outputs of the first and second amplifier die. A shunt circuit is coupled to the output of either or both of the first and/or second amplifier die. The shunt circuit includes a series coupled inductance and high-Q capacitor (e.g., a metal-insulator-metal (MIM) capacitor), and the shunt circuit is configured to at least partially resonate out the output capacitance of the amplifier die to which it is connected.

Abstract: A radar system comprising a transmitter controller, configured to control an oscillator such that the oscillator provides a transmit-radar-signal a transmit-first-overlapping-portion and a transmit-second-overlapping-portion that corresponds to the instantaneous frequency of the transmit-first-frequency-overlapping-portion. The transmitter controller is configured to reconfigure the oscillator from a first-operating-mode to a second-operating-mode between a transmit-first-ramp-frequency-portion and a transmit-second-ramp rising-frequency-portion. The radar system also includes a receiver controller configured to receive a received-radar-signal that represents a reflected version of the transmit-radar-signal, and provide a combined-overlapping-portion based on a combination of the transmit-first-overlapping-portion, the transmit-second-overlapping-portion, a received-first-overlapping-portion, and a received-second-overlapping-portion.

Abstract: A method for localizing a wireless node includes synchronizing a respective time reference of a plurality of wideband spectrum-sensing units and a master transceiver. A sensing location of each wideband spectrum-sensing unit is stored in a first memory. Each wideband spectrum-sensing unit stores in a second memory a plurality of time-limited samples of a transmission received from a slave transceiver. The time limit of the transmission is determined by the master transceiver, receiving the transmission. The samples from the second memory are correlated with a corresponding plurality of reconstructed samples stored in the first memory to form a respective power delay profile for each of the of the wideband spectrum-sensing units. A slave location of the slave transceiver is determined by applying a Time Difference Of Arrival method to the respective power delay profiles.

Abstract: An apparatus can include a first circuit that is configured to provide electrostatic discharge (ESD) protection against an ESD pulse applied between a first node and a second node. The first circuit includes a series stack of bipolar transistors that are configured to shunt current between the first and second nodes in response to the ESD pulse; and a diode connected in series with the stack of bipolar transistors and configured to lower a snapback holding voltage of the first circuit when shunting current between the first and second nodes.

Abstract: A matching network is integrated into a multilayer surface mount device containing an RFID integrated circuit to provide both an antenna and a matching network for the RFID integrated circuit in the ultra high frequency regime. The surface mount device may be mounted on a printed circuit board to provide RF and RFID functionality to the printed circuit board.

Abstract: A method for protecting configuration data from a data bus transceiver operable in a subnetwork mode. The configuration data are provided for comparison with data bus message data arriving via a data bus. A reference checksum for the configuration data is generated and stored, and recurrently checked. In the event of an identified alteration, a wake-up signal and/or a piece of error information is output. During or after writing the configuration data to a configuration register via the data bus or directly before the change to the low-power mode of the electronic control unit, a checksum unit forms a checksum that is stored in a reference register. In the low-power mode of the electronic control unit, the checksum for the configuration is repeatedly recomputed and compared with the checksum stored in the reference register. If the recomputed checksum does not match the stored checksum, a wake-up process is triggered.

Abstract: A Field Effect Transistor (FET) capable of operating at high frequencies and includes comb-shaped source and drain electrodes. The comb-shaped drain electrode includes a plurality of thin comb-shape drain electrode layers at corresponding levels of the FET, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped drain electrodes of each other layer. The comb-shaped source electrode includes a plurality of comb-shape source electrode layers at the corresponding levels, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped source electrodes of each other layer. In addition, the inter-level retraction of adjacent drain electrode layers is the same or substantially the same. Similarly, the inter-level retraction of adjacent source electrode layers is the same or substantially the same.

Abstract: The disclosure relates to an integrated circuit for a radio-frequency identification (RFID) tag. Example embodiments include an integrated circuit (101) for an RFID tag, the integrated circuit (101) comprising: a memory (104) for storing data; a transceiver (107) for receiving signals from, and transmitting signals to, an antenna (102); and a controller (103) configured to process signals received via the transceiver (107) and to access data stored in the memory (104); wherein upon receiving, via the transceiver module (107), a lock command referring to a data block in the memory (104), the controller (103) is configured to generate error correction data for the data block and to store the error correction data in the memory.

Abstract: An embedded system is described. The embedded system includes a processing circuit comprising at least one processor configured to support an implementation of a non-power-of-2 fast Fourier transform of length N using a multiplication of at least two smaller FFTs of a respective first length N1 and second length N2, where N1 and N2 are whole numbers; and a memory, operably coupled to the processing circuit and comprising at least input data.

Abstract: An electronic device includes a logic circuit, a pullup acceleration circuit, a first signal propagation path, and a second signal propagation path. The first signal propagation path propagates a logic value transition from an input terminal of the logic circuit to an output terminal of the logic circuit through the input terminal, two inverters of the logic circuit, a switch of the logic circuit, and the output terminal within a first amount of time based on a transition at the first input terminal. The second signal propagation path propagates the logic value transition from the input terminal to the output terminal through one inverter of the logic circuit and the pullup acceleration circuit within a second amount of time. The second amount of time is shorter than the first amount of time in response to the logic circuit being non-monotonic with respect to the logic value.

Abstract: An apparatus and method for resistive short circuit immunity for wheel speed sensor interface on a braking system. In one embodiment the apparatus includes a first circuit for generating a first periodic signal based on first current transmitted to a wheel speed sensor and a second circuit for generating a second periodic signal based on second current, some or all of which is received from the wheel speed sensor. A circuit is provided for selecting the first periodic signal for output if a magnitude of the second current is greater than a magnitude of the first current, or the second periodic signal for output if a magnitude of the second current is not greater than the magnitude of the first current. The selected first or second periodic signal contains information relating to a speed of a wheel that is associated with the wheel speed sensor.

Abstract: Embodiments of voltage regulators and methods for operating a voltage regulator are described. In one embodiment, a voltage regulator includes a power stage configured to convert an input direct current (DC) voltage into an output DC voltage, a driver device configured to drive the power stage, a timer configured to generate a constant on-time signal, a ripple generation device configured to generate a ripple signal, a comparator configured to perform voltage comparison in response to the ripple signal to generate an input to the timer, and a controller configured to generate a drive signal for the driver device in response to an inductor peak current in the voltage regulator and the constant on-time signal. Other embodiments are also described.

Abstract: A receiver circuit comprising an averaging-processing-block that is configured to receive an OFDM signal. The OFDM signal comprises a plurality of sample-values, wherein the sample-values comprise: a middle-sample-value; a lower-sample-value-group; and a higher-sample-value-group. The averaging-processing-block can determine an averaged-sample-value for the middle-sample-value by performing an averaging operation on the sample-values of the lower-sample-value-group and the higher-sample-value-group, but not on the middle-sample-value.

Abstract: The disclosure relates to range-determining-module for a transceiver, configured to: receive a signal comprising a received-data-packet, identify a plurality of known-sequence-sections of the received-data-packet, each known-sequence-section containing a known-data-sequence that is known to the range-determining-module; determine a reception-time-stamp associated with each of the plurality of known-sequence-sections; verify the received-data-packet using the reception-time-stamps associated with different respective known-sequence-sections of the received-data-packet; and provide a verified range estimate in accordance with one or more of the time stamps of the verified received-data-packet.