Abstract: An environmental parameter sensor for a mobile device is described comprising a first acoustic transducer; a second acoustic transducer arranged at a predetermined distance from the first acoustic transducer; a controller coupled to the first acoustic transducer and the second acoustic transducer; wherein the controller is configured to determine at least one of a time-of-flight value and an attenuation value of an acoustic signal between the first acoustic transducer and the second acoustic transducer and to determine at least one environmental parameter from the at least one of the time-of-flight value and the attenuation value The environmental parameter sensor may determine environmental parameters such as temperature, wind speed, and humidity from acoustic measurements.

Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.

Abstract: A peripheral controller, and method of operation, for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous, are described. A FIFO includes a FIFO controller and a FIFO memory and has a plurality of inputs. A multiplexer circuit is connected to the plurality of inputs, and is operable by a selection signal to supply either a first group of system and peripheral signals or a second group of system and peripheral signals to the FIFO to operate the FIFO to transmit data from the system to the peripheral or to receive data at the system from the peripheral.

Abstract: A universal serial bus (USB) link bridge device is disclosed. The USB link bridge device includes a host side module configured to be interfaced with a USB host. The host side module includes a receiver and is configured to receive serial data from the USB host, convert the received serial data into parallel data and store the parallel data into an elasticity buffer. A data controller coupled to the host side module is also included. The USB link bridge device further includes a device side module coupled to the data controller and includes a transmitter. The device side module is configured to receive parallel data from the data controller and convert the received parallel data into serial data and to transmit the serial data towards a USB device.

Abstract: In some embodiments a method of manufacturing a sensor system can comprise forming a first structure having a substrate layer and a first sensor that is positioned on a first side of the substrate layer, bonding a cap structure over the first sensor on the first side of the substrate layer, and depositing a first dielectric layer over the cap structure. After bonding the cap structure and depositing the first dielectric layer, a second sensor is fabricated on the first dielectric layer. The second sensor includes material that would be adversely affected at a temperature that is used to bond the cap structure to the first side of the substrate layer.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes a bipolar transistor device connected between a first node and a second node, a series protection device connected in series with the bipolar transistor device, and a diode device connected between the second node and a third node. A drain terminal of an NMOS device to be protected is connectable to the first node. A body of the NMOS device to be protected is connectable to the second node. A source terminal of the NMOS device to be protected is connectable to the third node. The diode device and the bipolar transistor device are configured to form a parasitic silicon controlled rectifier. Other embodiments are also described.

Abstract: A switch mode power supply is described including a primary side for coupling to a mains supply and a secondary side for coupling to a device, an isolation transformer comprising a primary coil and a secondary coil and arranged to isolate the primary side from the secondary side, and a noise filter coupled between a primary ground at the primary side and a secondary ground at the secondary side, the noise filter having a conductance value that varies with frequency. The noise filter conductance comprises a peak conductance in a peak conductance frequency region. The noise filter is operable to reduce the common-mode noise of the switch mode power supply at frequencies occurring in the peak conductance frequency region.

Abstract: The present application relates to an adaptive filter using manageable resource sharing and a method of operating the adaptive filter. The adaptive filter comprises a cluster controller configured for allocating each of several computational blocks to one of several clusters and a routing controller for configuring the routing of tapped delay signals by a routing logic to the respective cluster in accordance with an allocation of the tapped delay signals to the clusters. Each of computational blocks is configured for adjusting one filter coefficient, ci(n), in one cycle of an iterative procedure according to an adaptive convergence algorithm. The number of computational blocks is less than an order of the adaptive filter.

Abstract: A method of distinguishing a meaningful signal from a low frequency noise, such method includes: a first step of dividing an input acoustic signal into frames, a second step of calculating a power spectral density of the input acoustic signal for each frame and finding an envelope curve of the power spectral density, a third step of finding a predefined number of dominant peaks in the envelope curve found in the previous second step of the method, a fourth step of applying a linear regression algorithm to the dominant peaks to obtain a linear regression line for each frame and extracting a slope value of each linear regression line, a fifth step of identifying intervals (t1-t2, t3-t4) of the original acoustic signals including the meaningful signal as intervals which correspond to higher values of the slope value.

Abstract: An amplifier circuit comprising: a delta-PWM-modulator, a three-level-DAC, a loop-integrator, and a comparator. The delta-PWM-modulator receives a digital-input-signal; and processes the digital-input-signal and a modulator-triangular-signal to generate a delta-pulse-width-modulation-signal. The delta-pulse-width-modulation-signal is representative of the difference between a square-wave-carrier-signal and a digital-pulse-width-modulation of the digital-input-signal. The three-level-DAC receives the delta-pulse-width-modulation-signal from the delta-PWM-modulator and provides a three-level-analog-signal. The loop-integrator comprises: a virtual-ground-node-terminal configured to receive: (i) the three-level-analog-signal from the three-level DAC; and (ii) a feedback-signal from an output stage of the amplifier circuit via a feedback loop; and an integrator-output-terminal configured to provide a loop-integrator-output-signal.

Abstract: An integrated circuit includes a transmitter having a data input coupled to receive a single-ended data signal, a reference input coupled to receive a bandgap reference, a first differential output, and a second differential output. The transmitter is configured to, during normal operation, convert the single-ended data signal at the data input into a first differential signal at the first differential output and a second differential signal at the second differential output in which the first differential signal and the second differential signal are complementary to each other. A fault detection circuit is coupled to the first and second differential outputs and is configured to detect a load short fault condition and a bandgap short condition based on the first and second differential signals at the first and second differential outputs while forcing the data input to zero.

Abstract: An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.

Abstract: A near field communication (NFC) device capable of operating by being powered by the field includes an NFC module for generating an electromagnetic carrier signal and modulating the carrier signal, and an antenna circuit coupled to and driven by said NFC module with the modulated carrier signal. A differential power combiner circuit is coupled to said NFC module via output terminals of said NFC module. A powered by the field circuit of the NFC device is adapted to harvest energy from an external field to power said NFC device. The power by the field circuit has a first terminal coupled to an output of said differential power combiner circuit via a first impedance block and a second terminal coupled to an input of said antenna circuit via a second impedance block. The NFC device is adapted to be able to operate in a powered by the field card mode.

Abstract: The present application relates to a reconfigurable analog front-end circuit and a reconfigurable Ethernet transceiver with a reconfigurable analog front-end circuit. The circuit is reconfigurable using the at least one signal-path switching element controlled by a mode signal to operationally establish a first or a second signal path. The first signal path comprises an optional first signal-conditioning section and a shared ADC. The second signal path comprises an optional second signal-conditioning section, an upstream ADC and the shared ADC. The signal paths are selectively switched in response to a mode signal.

Abstract: An on-chip built-in self-test (BIST) circuit (10) uses a controller (16), analog-to-digital converter (ADC) (15), and digital-to-analog converter (DAC) (12) to sense voltage and/or temperature measures at predetermined circuit locations (19), to detect one or more idle states for an analog block during normal operation, to initiate a built-in self-test of the analog block during the idle state(s) by sending input test signals over a first bus (13) to the analog block, and to process analog test signals received over a second bus (14) from the analog block to generate digital built-in self-test results for the analog block so that the performance analyzer can analyze the digital built-in self-test results in combination with any voltage and/or temperature measurements to evaluate selected performance measures for the analog block against one or more performance criteria.

Abstract: A system includes a secure processor and an unsecure processor. The secure processor is configured to: split a secure scalar K into m2 random values ki, where i is an integer index; randomly select m1-m2 values ki for the indices m2<i?m1; select m1 mask values ?i; compute m1 residues ci based upon random residues ai, ??(i)?1, and k?(i), wherein ?(i) is a random permutation; compute m1 elliptic curve points Gi based upon random residues ai and an elliptic point to be multiplied; receive m1 elliptic curve points; and compute the elliptic curve scalar multiplication by combining a portion of the received elliptic curve points and removing the mask values ?i from the portion of the received elliptic curve points. The unsecure processor is configured to: receive m1 residues ci and elliptic curve points Gi; compute m1 elliptic curve points Pi based upon the m1 residues ci and elliptic curve points Gi; and send the m1 elliptic curve points Pi to the secure processor.

Abstract: Embodiments of a device and method are disclosed. A controller area network (CAN) device includes a compare module configured to interface with a CAN transceiver, the compare module having a receive data (RXD) interface configured to receive data from the CAN transceiver, a CAN decoder configured to decode an identifier of a CAN message received from the RXD interface, and an identifier memory configured to store an entry that corresponds to at least one identifier, and compare logic configured to compare a received identifier from a CAN message to the entry that is stored in the identifier memory and to output a match signal when the comparison indicates that the received identifier of the CAN message matches the entry that is stored at the CAN device. The CAN device also includes a signal generator configured to output, in response to the match signal, a signal to invalidate the CAN message.

Abstract: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.

Abstract: Upon receiving a request (203) in an initiator interface protocol identifying information to be returned in-order, an integrated circuit protocol bridge circuit device (200) allocates, to the ordered request, entries in a first ordered queue (e.g., 211) and a first static queue (e.g., 213) for the initiator interface protocol, generates a plurality of split target requests in a target interface protocol from the ordered request, and allocates the plurality of split target requests to entries in a second ordered queue (e.g., 217) and a second static queue (e.g., 218) for the target interface protocol, so that, upon receiving a plurality of out-of-order target responses, an allocated entry in the first ordered queue (211) for the first ordered initiator request is deleted only after a plurality of counter fields in the first static queue indicate that target responses have been received for all of the plurality of split target requests.

Abstract: A method and apparatus are provided for manufacturing a packaged electronic device (3) having pre-formed and placed through package circuit devices (35) which include an embedded circuit component (39) and conductor terminals (37A, 37B) extending from a molded package (38) embedding the circuit component (39). The through package circuit devices (35) are placed on end with integrated circuit die (34) and encapsulated in a molded device package (32) which leaves exposed the one or more conductor terminals (37A, 37B) positioned on first and second surfaces of the through package circuit device, where the conductor terminals (37A, 37B) and embedded circuit component (39) form a circuit path through the molded device package.