Abstract: An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. During a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit.

Abstract: An amplifier includes a supply voltage terminal and a reference voltage terminal and an input terminal. An amplifier arrangement includes a first and second branch coupled between the supply and reference voltage terminals, and one or more transistors configured to provide current flow through each of the branches based on the input signal at the input terminal. A first output terminal is coupled to the first branch to provide a first output signal based on the current flow therethrough. A second output terminal is coupled to the second branch to provide a second output signal based on the current flow therethrough. An impedance-modifying circuit is coupled to the second output terminal to provide a voltage variation in the second output signal in response to the input signal greater than a voltage variation in the first output signal in response to the input signal.

Abstract: A system with an integrated antenna includes a housing having a first surface and a second surface. The second surface of the housing defines a recess. A substrate is attached to first surface of the housing, and an amplifying device having an output node is on the substrate. An antenna is attached to the second surface of the housing over the recess. A conductive element is positioned through at least a portion of the housing. The conductive element electrically connects the antenna to the output node of the amplifying device. The conductive element is connected to the antenna at an antenna feed point over the recess in the housing.

Abstract: One example discloses a circuit for varying a quality-factor of a wireless device: wherein the wireless device includes an antenna tuning circuit and a communications signal interface; the circuit including, a quality-factor circuit having a feedback circuit; wherein the feedback circuit is configured to be coupled between the antenna tuning circuit and the communications signal interface; wherein the quality-factor circuit is configured to measure an antenna system bandwidth of the wireless device; and wherein the feedback circuit is configured to apply positive feedback to the antenna tuning circuit if the measured bandwidth is greater than a maximum communication signal bandwidth.

Abstract: An integrated circuit die that includes a temperature monitoring system that obtains measured temperature data from on die temperature sensors during a mode when power is not being supplied to a system controller of the die. After the system controller is powered up, the system controller obtains the measured temperature data. This system and method can be useful in that heat from a powered up system controller does not affect the temperature readings of the temperature monitoring system.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a semiconductor layer, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.

Abstract: Apparatus (103) suitable for determining the resistance and inductance of an electric motor (101) estimates the phase shift between a voltage applied to the motor and motor current. Estimation of the phase shift employs a heterodyne technique. The measured motor current is conditioned prior to heterodyning in a mixer 203 in order to reduce the effects of nonlinearities introduced by a voltage source inverter (102) which supplies the motor (101) with a voltage. A value for impedance may be calculated as a ratio of a voltage applied to the motor and the motor current. The resistance and inductance may then be calculated from the impedance and phase shift calculations. In cases where the voltage applied to the motor cannot be directly measured but only the voltage supply to the voltage source inverter 102 is known, a value for impedance may be determined based on a ratio of a reconstructed voltage signal having a phase angle equal to that of the motor current and the motor current.

Abstract: A signal processor comprising a plurality of microphone-terminals configured to receive a respective plurality of microphone-signals. A plurality of beamforming-modules, each respective beamforming-module configured to receive and process input-signalling representative of some or all of the plurality of microphone-signals to provide a respective speech-reference-signal, a respective noise-reference-signal, and a beamformer output signal based on focusing a beam into a respective angular direction. A beam-selection-module comprising a plurality of speech-leakage-estimation-modules, each respective speech-leakage-estimation-module configured to receive the speech-reference-signal and the noise-reference-signal from a respective one of the plurality of beamforming-modules; and provide a respective speech-leakage-estimation-signal based on a similarity measure of the received speech-reference-signal with respect to the received noise-reference-signal.

Abstract: There is described an electronic device, the device comprising (a) a power supply terminal for connecting to a power supply (130, 330), (b) a first circuit (110, 310) coupled to be powered by the power supply, the first circuit (110, 310) being susceptible to power supply noise within a predetermined frequency range, and (c) a second circuit (120, 320) coupled to be powered by the power supply, the second circuit (120, 320) comprising an open-loop capacitive DC-DC converter (323) having a switching frequency outside of the predetermined frequency range. There is also described a system comprising an electronic device and a reader/writer device. Furthermore, there is described a method of manufacturing an electronic device.

Abstract: A pulse laser test system including a conditioning pulse circuit, a probe pulse circuit, a pulse laser, a trigger mode controller, and a laser pulse modulator. The conditioning pulse circuit provides asynchronous conditioning trigger pulses at a selected rate. The probe pulse circuit provides a synchronized probe trigger pulse. The trigger mode controller selects the probe pulse circuit while the synchronized probe trigger pulse is provided causing the pulse laser to provide a synchronized probe laser pulse, and otherwise selects the output of the conditioning pulse circuit causing the pulse laser to provide asynchronous conditioning laser pulses. The laser pulse modulator has an optical input coupled to the laser output of the pulse laser, has a gating input receiving a gate signal from the trigger mode controller, and has an optical output that provides laser pulses passed from the pulse laser while the gate signal is asserted.

Abstract: Methods and systems are disclosed for stateful backend drivers for security processing through stateless virtual interfaces within virtual machine (VM) host servers. A security application runs within a hosted VM, and a header is stored for the security application that includes a host backend identifier (BID). The VM sends a security processing request including the header through a stateless virtual interface to a backend driver. The backend driver compares the host BID within the processing request to host BIDs associated with the VM host server. If a match is found, security processing request is performed using one or more security engines within the VM host server. If a match is not found, the VM is identified as a migrated VM, and the header is updated to store a host BID associated with the VM host server. A timestamp for virtual queue creation is preferably used for the host BID.

Abstract: A semiconductor device composed of a through-substrate-via (TSV) interconnect, and methods for forming the interconnect.

Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.

Abstract: A packaged unidirectional power transistor comprises a package with a number of pins which provide a voltage and/or current connection between the outside and the inside. Inside the package, a bidirectional vertical power transistor is present with a controllable bidirectional current path, through a body of the bidirectional vertical power transistor, between a first current terminal of the bidirectional vertical power transistor connected to the first current pin and a second current terminal of the bidirectional vertical power transistor connected to the second current pin. A control circuit connects the control pin to the body terminal and the control terminal to drive the body and the control terminal, which allows current through the body in a forward direction, from the first current terminal to the second terminal, as a function of the control voltage, and to block current in a reverse direction regardless of the voltage.

Abstract: A current source circuit includes a first variable resistor circuit. The first variable resistor circuit includes a resistive material and a first plurality of tap inputs configured to set a resistance of the first variable resistor circuit. The current source circuit includes an output configured to provide a current. The current is adjustable by varying the resistance of the first variable resistor circuit. The current source circuit includes a second variable resistor circuit. The second variable resistor circuit includes a resistive material of a same resistive material type as the resistive material of the first variable resistor circuit. The second variable resistor circuit includes a second plurality of tap inputs configured to set a resistance of the second variable resistor circuit. Each tap resistance of the second variable resistor circuit is proportional to a corresponding tap resistance of the first variable resistor circuit.

Abstract: A body-control-device for a bi-directional transistor, said bi-directional transistor having a first-transistor-channel-terminal, a second-transistor-channel-terminal, a transistor-control-terminal and a transistor-body-terminal. The body-control-device comprises a body-control-terminal connectable to the transistor-body-terminal of the bi-directional transistor, a first-body-channel-terminal connectable to the first-transistor-channel-terminal of the bi-directional transistor, a second-body-channel-terminal connectable to the second-transistor-channel-terminal of the bi-directional transistor, a negative-voltage-source and a switching-circuit configured to selectively provide an offset-first-circuit-path between the first-body-channel-terminal and the body-control-terminal, wherein the offset-first-circuit-path includes the negative-voltage-source such that it provides a negative voltage bias between the body-control-terminal and the first-body-channel-terminal.

Abstract: A semiconductor device includes a trimming circuit for a power management circuit. The trimming circuit includes an analog to digital converter (ADC) circuit with a comparator circuit, a successive approximation register (SAR) circuit having an input coupled to an output of the comparator circuit, a control circuit coupled to the SAR circuit, a digital to analog converter (DAC) circuit having inputs selectively couplable to digital output signals of the SAR circuit and an output coupled to a first input of the comparator circuit, and a variable resistance circuit configured to be selectively coupled to output signals of the ADC circuit.

Abstract: An integrated circuit includes clock suppression circuitry that can suppress the launch pulse of an at-speed test to prevent scan test data from propagating from an output of a scan latch through a multi-clock cycle combinational logic path to a downstream scan latch during the at-speed test. The integrated circuit can also suppress the capture pulse of an at-speed test to prevents scan test data that is propagated from an upstream scan latch through a multi-cycle combinational logic path from being latched at the downstream latch during the at-speed test.

Abstract: A device can be configured to provide isolation between conductive circuit paths and to selectively connect one of the conductive circuit paths to a shared interface. Each conductive circuit path can include driver circuitry designed to transmit signals according to a particular protocol and a corresponding signal speed. The shared interface can be, in one instance, a connector designed for connection to other devices. The other devices can be configured to communicate over the shared interface using one or more of the particular protocols provided using the different circuit paths.

Abstract: One example discloses an apparatus for wireless communication, including: a first wireless device configured to communicate with a second wireless device over a first wireless link, according to a first wireless link protocol; wherein the first wireless link protocol defines communications between the first wireless device and the second wireless device; wherein the first wireless device is configured to monitor communications on a second wireless link between the second wireless device and a third wireless device; wherein the second wireless link is configured according to a second wireless link protocol that defines communications between the second wireless device and the third wireless device; and wherein the first wireless device is configured to spoof the second wireless device in response to an error condition or signal degradation on the second wireless link.