Abstract: A secondary side controller for a power converter configured to provide a control signal to an emitter element of an opto-coupler for control of a primary side controller of the power converter, the secondary side controller configured to operate with the primary side controller for controlling the voltage output of the power converter, the secondary side controller configured to, based on; a first control value configured to instruct the power converter to output its present voltage output; and a second control value configured to instruct the power converter to provide a requested target voltage output; provide said control signal in accordance with a transition profile over a predetermined transition time period to effect a change between the first control value and the second control value, the transition profile comprising at least a first rate of change in the control signal followed by an end time period leading to the end of the transition time period during which the rate of change in the control

Abstract: One example discloses a component carrier, including: a cavity; wherein the cavity includes a set of cavity registration features configured to engage with a set of component registration features on a component; and wherein the cavity registration features are within the cavity.

Abstract: An integrated circuit for protecting against transient electrical stress events includes a rail clamp device, and a trigger circuit including a resistive-capacitive (RC) filter, a drive circuit including a first inverter stage receiving an input signal from the RC filter, the drive circuit is configured to enable the rail clamp device during a transient electrical stress event, and a stress event detection circuit coupled to the RC filter. The drive circuit includes a configurable activation voltage which is controlled by the stress event detection circuit, wherein the activation voltage is reduced when the transient electrical stress event is detected.

Abstract: One example discloses a near-field electromagnetic induction (NFEMI) antenna, including: an electric antenna including a first electrically conductive surface; a magnetic antenna including a first coil (L1) coupled to a second coil (L2); a first feeding connection coupled to one end of the first coil; a second feeding connection coupled to another end of the first coil and one end of the second coil; wherein a another end of the second coil is connected to the electrically conductive surface; and a magnetic permeable material coupled to one side of the magnetic antenna and configured to be placed between the magnetic antenna and a set of electric components.

Abstract: A method and apparatus for handling outstanding interconnect transactions between a master device and an interconnect component. For example, a transaction intervention module coupled to an interconnect component and a master device of the interconnect component. The transaction intervention module is arranged to receive an indication of a functional state of the master device. If the master device is indicated as being in a faulty functional state the transaction intervention module is further arranged to determine whether any interconnect transactions initiated by the master device with the interconnect component are outstanding. If it is determined that at least one interconnect transaction initiated by the master device is outstanding, the transaction intervention module is arranged to finalize the at least one outstanding interconnect transaction with the interconnect component.

Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx 164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI Interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.

Abstract: A receiver decodes received data streams based on a subset of candidate decoding constellation points. A first stage of a decoder of the receiver selects a subset of candidate decoding constellation points by identifying a decoded value for an initial data stream of the set of data streams. A second stage then applies MMSE error detection to each of the constellation points in the selected subset, and calculates an error metric based on the MMSE error detection results. The decoder selects the constellation points having the lowest error metrics, and uses the selected constellation points as an initial set of points for decoding the next data stream to be decoded.

Abstract: The invention provides a bond wire arrangement comprising a signal bond wire (1) for operably connecting a first electronic device (6) to a second electronic device (8), and a control bond wire (2) being arranged alongside the signal bond wire at a distance so as to have a magnetic coupling with the signal bond wire (1), and having a first end (11) coupled to ground, and a second end (12) coupled to ground via a resistive element (14). The proposed solution allows the control of the Q factor (losses) of wire bond inductors during assembly phase, which will save time and reduce overall design cycle as compared to known methods.

Abstract: Electrostatic discharge (ESD) protection circuitry in an integrated circuit is provided. The protection circuitry includes a trigger circuit coupled between a first power supply bus and a second power supply bus. A delay circuit is coupled to receive an output signal from the trigger circuit. The delay circuit includes a first inverter coupled to the input of the delay circuit and a feedback transistor having a control terminal coupled to the output of the delay circuit, a first current electrode coupled to the first power supply bus, and a second current electrode coupled to the output of the first inverter. A clamp driver circuit is coupled to the output of the delay circuit.

Abstract: The embodiments described herein provide communication devices and methods that can facilitate communication between galvanically isolated systems. Specifically, the embodiments facilitate communication to a galvanically isolated system that is shut down without requiring that this shutdown system consume its own power while it is shutdown. To facilitate this, the communication devices and methods provide a wake-up device on the side of the shutdown system and facilitate the transfer of power across the galvanic isolation to the wake-up device when communication to the shutdown system is needed. With the wake-up device powered using power that was transferred across the galvanic isolation, the wake-up device can perform the actions needed to wake up the shutdown system, and can thus facilitate communication between the galvanically isolated systems. Thus, communication between galvanically isolated systems is facilitated without requiring that the shutdown system consume its own power during shutdown periods.

Abstract: Semiconductor devices include a semiconductor substrate containing a source region and a drain region, a gate structure supported by the semiconductor substrate between the source region and the drain region, a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range, and a well region in the semiconductor substrate. The well region has a second conductivity type and is configured to form a channel therein under the gate structure during operation. Methods for the fabrication of semiconductor devices are described.

Abstract: According to a first aspect of the present disclosure there is provided a game board being arranged to accommodate at least one game piece, said game board comprising at least one NFC device and a plurality of NFC antennas which are operatively coupled to said NFC device, wherein said NFC device is arranged to activate a function of said game piece by establishing NFC with the game piece through one of said antennas. According to a second aspect of the present disclosure a corresponding method for activating at least one game piece on a game board is provided. According to a third aspect of the present disclosure there a corresponding computer program product is provided.

Abstract: As may be implemented in a manner consistent with one or more embodiment, aspects of the disclosure are directed to latency control with signals, such as audio signals. For instance, a quality characteristic of an audio signal having time-sequenced frames exhibiting a signal quality can assessed, and an output indicative of the signal quality is provided based on the assessment. An amount of latency in the audio signal is dynamically adjusted based on the output, and the latency can be used in processing the time-sequenced frames, such as to use future frames in assessing or correcting a current frame during a time period facilitated via the latency.

Abstract: A current regulator circuit to improve electromagnetic compatibility performance operation of an IC device includes an input to receive a regulated voltage signal, an output to provide an output voltage at a desired voltage level, the output voltage exhibiting noise from a load, a first field effect transistor FET including a first source electrode coupled to the input, a first drain electrode coupled to the output, and a first gate electrode, a voltage clamp circuit coupled to the output, the voltage clamp circuit configured to conduct a varying current based upon the noise, a constant current source to provide a constant current, and a second FET including a second source electrode coupled to the output, a second drain electrode coupled to the constant current source and to the first gate electrode, and a second gate electrode coupled to the voltage clamp circuit to mirror the varying current in the second FET.

Abstract: A power converter including a power conditioning circuit to receive input power and set operating voltages of the power converter, a current sensing circuit to determine an input current of the power converter, a voltage regulation circuit to step down a voltage level of the input power, a charge pump circuit to store charge delivered by the voltage regulation circuit and output to a load a current larger than the input current, and a power path controller to control switching and provide feedback within the power converter.

Abstract: The embodiments described herein provide analog-to-digital converters and methods that can reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals while still providing the ability to perform an accurate analog-to-digital conversion. In general, the embodiments described herein reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals by pre-charging the sampling capacitor used in the conversion. For example, the embodiments can apply the buffered input signal apply to the sampling capacitor for a first sampling cycle to pre-charge the sampling capacitor, and then directly apply the unbuffered input signal to the sampling capacitor for a second sampling cycle to final-charge the sampling capacitor. With the sampling capacitor charged using the two stage charging, a digital output corresponding to the charge of the sampling capacitor is generated.

Abstract: A system on a chip (SoC) and method of operation are described. A data processor has a processor data word size of p×octets and is configured to handle data items having a data item size which is a non-integer multiple of the processor data word size. A memory controller is configured to write or read data items to a memory as multiples of m×octets. Data can be sent between the data processor and the memory controller on a bus. A data protection code generator is configured to generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address. A data protection code checker is configured to receive a read data protection code and a read data item and to check the read data item for an error using the read data protection code.

Abstract: According to an aspect of the invention a method for calibrating a measurement device is conceived wherein: a calibration device is brought into close proximity of the measurement device such that a data communication link is established between the measurement device and the calibration device; wherein the following steps are performed while the calibration device and the measurement device are in close proximity of each other: the calibration device performs a measurement of at least one physical phenomenon; the measurement device performs a measurement of the same physical phenomenon; the result of the measurement by the measurement device is compared with the result of the measurement by the calibration device; and calibration parameters are computed based on a difference between the result of the measurement by the measurement device and the result of the measurement by the calibration device.

Abstract: A pressure sensor includes a diaphragm suspended across a cavity in a substrate. A first group of piezoresistors is provided in the diaphragm proximate a first outer edge of the diaphragm, the piezoresistors of the first group being coupled to one another to form a first Wheatstone bridge. A second group of piezoresistors is provided in the diaphragm proximate a second outer edge of the diaphragm, the piezoresistors of the second group being coupled to one another to form a second Wheatstone bridge. The first and second Wheatstone bridges exhibit mirror symmetry relative to one another. Output signals from each of the first and second Wheatstone bridges are processed at respective first and second differential amplifiers. The output signals from each of the first and second differential amplifiers are processed at a third differential amplifier to produce a pressure output signal with enhanced sensitivity and reduced impact from process variation.

Abstract: An FFT device for performing a Fast Fourier Transform (FFT) is described. The FFT device comprises: a control unit arranged to control a sequence of transformation rounds; and a coefficient unit for providing transformation data; and a transformation unit arranged to receive the transformation data and to perform the respective linear transformation on the basis of the transformation data. The coefficient unit comprises or is integrated in a Random Access Memory (RAM) unit, the RAM unit comprising a set of memory blocks. The set of memory blocks comprises: a subset of window memory blocks or a subset of window-FFT memory blocks. The set of memory blocks further comprises a subset of FFT memory blocks providing a set of twiddle coefficients or a reduced set of twiddle coefficients.