Abstract: A design tool system includes a schematic design tool that computes a total number of devices in an analog circuit schematic based on information extracted from the analog circuit schematic. The schematic design tool selects an optimal row/column device configuration for the total number of devices and creates a temporary layout based upon the optimal row/column device configuration. The schematic design tool computes layout structure data based on the temporary layout and provides the layout structure data to a place and route tool within the design tool system that, in turn, generates a layout based on the layout structure data The design tool system then generates mask layer data based upon the layout that is configured to generate masks for construction of an integrated circuit corresponding to the analog circuit schematic.

Abstract: Microelectronic systems having integrated heat dissipation posts are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the step or process of obtaining a microelectronic component from which a heat dissipation post projects. The microelectronic component is placed or seated on a substrate, such as a multilayer printed circuit board, having a socket cavity therein. The heat dissipation post is received in the socket cavity as the microelectronic component is seated on the substrate. Concurrent with or after seating the microelectronic component, the microelectronic component and the heat dissipation post are bonded to the substrate. In certain embodiments, the heat dissipation post may be dimensioned or sized such that, when the microelectronic component is seated on the substrate, the heat dissipation post occupies a volumetric majority of the socket cavity.

Abstract: A power switch module comprising a control component. Upon an indicated operating condition fulfilling a protection condition, the control component is arranged to transition the power switch module from an ON state to a latched-OFF state in which the control component is arranged to configure the switching device to be turned off to decouple the load node from the power supply node. Having transition to the latched-Off state, the control component is further arranged to determine whether a voltage level at the load node exceeds a threshold voltage level, and if it is determined that the voltage level at the load node exceeds the threshold voltage level, transition the power switch module from the latched-OFF state to a current-limited state in which the control component is arranged to control the switching device to limit current-flow there through.

Abstract: The embodiments described herein provide wideband highly asymmetrical power efficient amplifier device that include a compact input power distribution network with input termination circuit. The input termination circuit is configured to provide control of the power distribution at the amplifier input. In one embodiment, the input termination circuit is configured to generate and reflect a frequency dependent portion of an input signal back toward the amplifier device inputs. This input reflection controls the input power distribution and shape of time domain input signal in a way that can affect amplifier device efficiency and linearity.

Abstract: A turbo decoder decodes encoded data using a regenerated interleaver sequence. An addressable column index memory stores column indexes of the encoded data during an input phase of a turbo decode operation. An address generator generates the regenerated interleaver sequence based on the column indexes and computed data. In embodiments the address generator can read column indexes from the addressable column index memory, compute the computed data by permuting row indexes in a same row permuting order as an encoder that encoded the encoded data, combine the column indexes so read and the row indexes so permuted, use a row counter, and identify out of bounds addresses using the regenerated interleaver sequence.

Abstract: A level shifter circuit is described herein for shifting a signal from a first voltage domain to a second voltage domain. The level shifter circuit includes two current paths between a supply terminal of the first voltage domain and a supply terminal of the second voltage domain. The first and second current paths each include a differential transistor that receives a signal from a pulse generator in a first voltage domain. The pulse generator provides pulses to the differential transistors based on an input signal to be translated to the second voltage domain. The level shifter includes a latch circuit in the second voltage domain that includes two inputs where each input is biased at a node of one of the current paths. Each current path includes a bias transistor whose control terminal receives a compensated biasing voltage for biasing the bias transistor. The compensated biasing voltage is compensated to account for drive strength variation of at least one transistor in each current path.

Abstract: A system on a chip comprising: a first communication controller; at least one second communication controller operably coupled to the first communication controller; at least one processing core operably coupled to the first communication controller and arranged to support software running on a first partition and a second partition; and a virtual machine monitor located between the first and second partitions, and the at least one processing core and arranged to support communications there between. The first communication controller is arranged to: generate or receive at least one data frame; and communicate the at least one data frame to the at least one second communication controller; such that the at least one second communication controller is capable of routing the at least one data frame to the second partition bypassing the virtual machine monitor.

Abstract: A system includes sensor modules, each associated with a wheel on a vehicle, and a receiver unit. Each sensor module calculates a rotation period associated with the wheel during turn mode vehicular motion and determines rotation direction of the associated wheel during straight vehicular motion. A data packet that includes a unique identifier for the sensor module, the rotation period, and the rotation direction are transmitted from each sensor module for receipt at the receiver unit. The receiver unit determines the steered wheels and non-steered wheels based on the rotation period, and the receiver unit can determine which wheels are on the right side or the left side of the vehicle based on the rotation direction. Knowledge of the steered and non-steered wheels and the rotation direction of the wheels, enables the receiver unit to assign locations of the sensor modules, and hence positions of the wheels of the vehicle.

Abstract: A radio frequency (RF) chip capacitor circuit and structure are provided. The circuit and structure include a plurality of capacitors connected in series. Each capacitor of the plurality includes a first plate formed from a first metal layer and a second plate formed from a second metal layer. A first two adjacent capacitors of the plurality include first plates formed in a first contiguous portion of the first metal layer or second plates formed in a second contiguous portion of the second metal layer. Each capacitor of the plurality may include a dielectric layer disposed between the first plate and the second plate.

Abstract: In accordance with at least one embodiment, a processor system is disclosed having a SIMD processor device that has a plurality of subsidiary processing elements that are controlled to process multiple data concurrently. In accordance with at least one embodiment, the SIMD processor is a vector processor (VPU) having a plurality of vector Arithmetic Units (AUs) as subsidiary processing elements, and the VPU executes an instruction to transfer table information from a global memory of the VPU to a plurality of local memories accessible by each AU. The VPU also executes an instruction that results in each processing element performing a table lookup from a table stored at its local memory. In response to the instruction, this table lookup uses a portion of a lookup value to access information from the table, and uses another portion of the lookup information to calculate an interpolated resultant based upon the accessed information.

Abstract: A DMA controller includes a built-in timing sequence generator that allows the DMA controller to trigger data movement periodically and/or non-equidistantly, without waking a CPU or other peripherals.

Abstract: A circuit comprises an amplifier, a first switch arranged between an amplifier input and an amplifier output, a first capacitor, a first resistor, a second switch, a third switch, a first converter coupled to the first amplifier output, a register storing a last digital value, a second converter converting the stored last digital value into a corresponding voltage value, and a control circuit. The control circuit charges the first capacitor to the corresponding voltage value by coupling a second converter output to a second capacitor terminal and switching on the first switch, or by coupling the second converter output to the first capacitor terminal and switching on the third switch; switches on the first switch and the second switch for providing the input voltage signal to the first capacitor; and switches on the third switch for determining a subsequent digital value of the converted output amplifier signal.

Abstract: A switched capacitor power converter comprising: an input terminal; an output terminal; a plurality of capacitors; a plurality of switches for selectively connecting the plurality of capacitors to each other, and/or to the input terminal, and/or to the output terminal; and a controller configured to operate the plurality of switches based on an output voltage, such that one or more of the plurality capacitors are connected between the input terminal and the output terminal as either: a first-topology, to provide a first conversion ratio; or a second-topology, to provide a second conversion ratio, wherein the second conversion ratio is different to the first conversion ratio.

Abstract: A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. The packet processor generates a transmit control configuration packet, which includes the control data. The control-frame processor inserts the transmit control configuration packet into a first control frame, outputs the control frame to the interface and extracts a receive-configuration packet from a second control frame for generating one or more interrupts. The mode selector generates mode and idle signals for determining the mode of the interface, based on the idle signal. In one implementation, the system uses JESD control frames to reduce GPIO pin usage.

Abstract: A pressure sensor includes a diaphragm suspended across a cavity in a substrate. A first group of piezoresistors is provided in the diaphragm, the piezoresistors of the first group being coupled to one another to form a first Wheatstone bridge having first positive and negative output nodes. A second group of piezoresistors is provided in the diaphragm, the piezoresistors of the second group being coupled to one another to form a second Wheatstone bridge having second positive and negative output nodes. The first negative output node of the first Wheatstone bridge is electrically connected to the second positive output node of the second Wheatstone bridge to directly chain the outputs of the Wheatstone bridges. The first and second Wheatstone bridges each produce an output signal as a function of an external pressure stimulus that is combined via the chained arrangement of the Wheatstone bridges to produce a composite output signal.

Abstract: A method includes performing an ion beam etching process on a tunnel magnetoresistance (TMR) stack to remove material portions of a first magnetic layer and a tunnel barrier layer of the TMR stack. The ion beam etching process stops at a top surface of a second magnetic layer of the TMR stack. A protective layer is deposited over the TMR stack. Another etch process is performed to remove the protective layer such that a portion of the second magnetic layer is exposed from the protective layer and a spacer is formed from a remaining portion of the protective layer. The spacer surrounds sidewalls of the first magnetic layer and the tunnel barrier layer. The portion of the second magnetic layer exposed from the protective layer is removed so that a TMR sensor element remains, where the TMR sensor element includes a bottom magnet, a top magnet, and a tunnel junction.

Abstract: A delay-locked loop (DLL) includes a delay line configured to receive a reference clock signal and a control signal, and generate a first plurality of clock signals. Each clock signal of the first plurality is configured to have a different phase delay relative to the reference clock signal. A phase frequency detector is coupled to the delay circuit and is configured to receive a first clock signal and a second clock signal of the first plurality, and generate up and down control signals. A charge pump is coupled to receive the up and down control signals and generates a charge pump current based on the up and down control signals. An output of the charge pump is coupled to the delay line at a voltage control node. An initialization circuit is coupled to the voltage control node and is configured to generate an initialization voltage based on the reference clock signal frequency.

Abstract: A semiconductor device and a method for making the semiconductor device are provided. The method of making the semiconductor device may include patterning a layer for a first conductor and a second conductor, plating patterned portions of the layer to form the first conductor and the second conductor, removing patterned material to form an air gap between the first conductor and the second conductor, applying a self-supporting film on top of the first conductor and the second conductor to enclose the air gap, and reacting the self-supporting film causing the self-supporting film to be substantially non-conductive.

Abstract: A system comprises at least one magnetic field sensor having a magnetic sense element formed on a substrate. The sense element senses a magnetic field along a sense axis oriented in a first direction parallel to a surface of the substrate. A shield structure is formed on the substrate. The shield structure has first and second shield portions and the magnetic sense element is disposed between the shield portions. Each of the shield portions includes a body and first and second brim segments extending from opposing ends of the body. The body is aligned parallel to a second direction perpendicular to the first direction and parallel to the surface of the substrate. The brim segments are aligned substantially parallel to the first direction. The shield portions are arranged in mirror symmetry with the brim segments of each of the shield portions extending toward one another.

Abstract: An isolation cell clamps a signal passing from a first, powered-down power domain to a second, power-on power domain. To reduce leakage current, some of the circuits and devices are connected to a voltage supply of the first or “from” power domain, while other circuits and devices are connected to a voltage supply of the second or “to” power domain.