Abstract: A method of fabricating a 3D fan-out structure for an integrated circuit device includes providing a substrate carrier having first and second opposing surfaces and an aperture extending between the first and second surfaces. A first semiconductor die is bonded to the first surface of the substrate carrier such that the first die covers the aperture of the substrate carrier. An encapsulant and a second die are deposited within the aperture of the substrate carrier such that an active surface of the second die is exposed and coplanar with the second surface of the substrate carrier. One or more redistribution layers are then applied on the second surface of the substrate carrier to form a 3D fan-out structure.

Abstract: A layer selection module for a graphics display component, and method therefor. The layer selection module is arranged to identify a set M of active layers to be blended for a pixel, configure a display controller to generate composite pixel data for the pixel based on a subset N of up to n layers from the set M, determine whether a number m of active layers in the set M exceeds n, and output an indication of which active layers within the set M were excluded from the subset N, if it is determined that the number m of layers in the set M exceeds n.

Abstract: A constellation mapping method, system, and apparatus are provided for mapping a received bit stream of data to a higher order symbol vector by processing a first set of selected bits from the received bit stream with a quadrant selector to identify a first quadrant offset vector corresponding a higher order quadrant in which an intended symbol is to be mapped, processing a second set of selected bits from the received bit stream with a 16-QAM mapper to identify a 16-QAM symbol vector, transforming the 16-QAM symbol vector into a transformed 16 QAM symbol vector based on the identified higher order quadrant, and combining the transformed 16-QAM symbol vector with the first quadrant offset vector to map the bit stream of data to a higher order symbol vector.

Abstract: A CAN bus system that permits a slave node to be connected to the CAN bus. The slave node uses a preamble of a data frame transmitted by the master node on the bus to generate an internal CAN sampling clock. The slave node over-samples frames transmitted over the bus, and monitors the sampled data for a predetermined pattern, which is used to generate the slave node CAN sampling clock. Thus, the slave node does not require or include an external crystal for generating its CAN sampling clock.

Abstract: A memory controller includes a clock delay generator, a set of flip-flops, and a control circuit, and is connected to a processor and a memory. The clock delay generator receives a clock signal from the processor, delays the clock signal by a set of delay time intervals, and generates a set of delayed clock signals. The flip-flops receive a test pattern and read data from the memory, sample the test pattern and the read data based on the delayed clock signals, and generate a set of sampled test patterns and a set of sampled read data. The control circuit identifies a sampled test pattern that is equal to the test pattern and the corresponding delayed clock signal as a read clock signal, and outputs the sampled read data that corresponds to the (delayed) read clock signal.

Abstract: Various embodiments include a network manager for managing network keys in a network having a plurality of nodes, the device including: a memory; and a processor configured to: determine N nodes to blacklist, wherein N is an integer; select a polynomial function from a plurality of polynomial functions of degree K and wherein the polynomial functions define plurality of secret network keys; generate K-N random abscissa values, wherein none of the random abscissa values are not found in a list of node abscissa values; calculate K-N polynomial function values for the K-N random abscissa values; calculate N polynomial function values for N node abscissa values associated with the N blacklisted nodes; transmit a message to nodes in the network including an indication of the selected polynomial function, the K-N random abscissa values, the N node abscissa values associated with the N blacklisted nodes, the K-N calculated polynomial function values, and the N calculated polynomial function values.

Abstract: A network processor has a “bi-level” architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. Each classification algorithm engine generates one or more single-record search requests to search the hash database for classification information based on one or more field values of the received packet or other classification parameters. Each single-record search requests is provided to the single-record search level, which executes the requests at the hash database and returns the corresponding record to the requesting classification algorithm engine.

Abstract: A communications system comprising a master-node and a slave-node. The master-node comprising: a GNSS receiver configured to provide a GNSS based time reference signal; a master-timing-reference-calibrator configured to determine a master-timing-reference-calibration-signal, for calibrating the master reference timing circuit, based on the GNSS based time reference signal; and a master-reference-timing-circuit configured to provide a master-clock-signal based on the master-timing-reference-calibration-signal, wherein the master-clock-signal is a clock signal for the master-node; and a master-transmitter configured to determine a master-communications-signal using the master-clock signal.

Abstract: A constellation mapping method, system, and apparatus are provided for mapping a received bit stream of data to a higher order symbol vector by processing a first set of selected bits from the received bit stream with a quadrant selector to identify a first quadrant offset vector corresponding a higher order quadrant in which an intended symbol is to be mapped, processing a second set of selected bits from the received bit stream with a 16-QAM mapper to identify a 16-QAM symbol vector, transforming the 16-QAM symbol vector into a transformed 16 QAM symbol vector based on the identified higher order quadrant, and combining the transformed 16-QAM symbol vector with the first quadrant offset vector to map the bit stream of data to a higher order symbol vector.

Abstract: One example discloses a combination wireless charging and communications device, including: a series reactance; wherein the series reactance is configured to be coupled in series between an antenna and a charging circuit; wherein the series reactance is configured to conduct a charging current between the antenna and the charging circuit; a parallel reactance; wherein the parallel reactance is configured to be coupled in parallel with the antenna and a communications circuit; and wherein the parallel reactance is configured to conduct a communications voltage between the antenna and the communications circuit.

Abstract: One example discloses an antenna tuning device, including: a controller configured to be coupled to a transceiver having an antenna tuner; wherein the transceiver is coupled to an antenna; wherein the controller is configured to receive a measured current signal from the transceiver corresponding to a current sent to or received by the antenna; and wherein the controller is configured to change an impedance of the antenna tuner in response to the measured current signal.

Abstract: One example discloses a near-field device, configured to receive a non-propagating quasi-static near-field signal from a near-field antenna, including: a tuning circuit including a first impedance tuning bank and a second impedance tuning bank; a controller configured to, detect when the device is in an idle-state; set the first impedance tuning bank and the second impedance tuning bank to an initial set of values; bring the near-field antenna and the near-field device combination to a frequency within a near-field signal bandwidth by adjusting the first and/or second impedance tuning banks; measure a first received signal strength; and differentially adjust the first and second impedance tuning banks until a measured second received signal strength is less than the first received signal strength.

Abstract: An apparatus includes a processor configured to receive first sensor data from a sensor system of the first entity and a receiver. The receiver is configured to receive second sensor data from a second entity in the vehicle to vehicle network over a communication network and provide the second sensor data to the processor. The second sensor data comprises a first type of sensor data having a first bandwidth requirement. The processor is further configured to determine an available bandwidth of the communication system; and when the first bandwidth requirement exceeds the communication bandwidth, select a second type of sensor data having a second bandwidth requirement. The second bandwidth requirement is less than the first bandwidth requirement. The processor is further configured to process the first and second sensor data to at least partially determine an environment surrounding the first entity.

Abstract: A millimeter-wave wireless multiple antenna system (200) is provided in which a UE (210) uses a multi-antenna subsystem (211) to sweep a plurality of receive beams (RX1-RXM) during each transmit beam in a plurality of transmit beams (TX1-TX64) used by the base station (201) to transmit an SSB, and then generates, for each receive beam, a received signal strength indicator (RSSI) value from samples of each transmitted SSB measured in said receive beam, thereby generating a plurality of RSSI values from which an optimal receive beam is selected based on a ranking of the RSSI values and then used to lock the UE (210) onto the optimal receive beam to perform a cell search which matches a transmit beam from the base station (201) to the optimal receive beam.

Abstract: A delay circuit, including a connector pad to receive a data input, a pad pin to receive a clock input having a clock edge, a first data line to receive the data input, a second data line to receive the data input, the second data line including a delay circuit that outputs a delayed data output, and at least one logic gate to accept the data input and delayed data output and output a logic state, wherein the logic state determines whether there is a glitch in the delayed data output, and wherein the delay circuit includes at least one delay element to register an output of the at least one logic gate at the clock edge to recognize the glitch.

Abstract: Aspects of the present disclosure are directed to an antenna, various implementations and methods therefor. Various embodiments are amenable to implementation with a receiver circuit that harvests power using energy from a radio frequency (RF) signal received, and a near-field communication (NFC) circuit. A first antenna collects and presents the RF signal to the receiver circuit, and a second antenna communicates NFC signals for the NFC circuit using an antenna portion shared with the first antenna.

Abstract: A system may include a radio frequency (RF) amplifier device that includes an input impedance matching network and first and second baseband decoupling circuits, which may remove intermodulation distortion products from signal energy input to the RF amplifier device at baseband frequencies. The input impedance matching network may act as a band-pass or low-pass filter. A gate bias voltage may be applied to the gate of a transistor in the RF amplifier device through one of the baseband decoupling circuits or, alternatively, at an input node of the RF amplifier device.

Abstract: A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.

Abstract: A semiconductor device that includes a semiconductor structure having a side wall that is non planar and that extends farther outward at an upper portion than at a lower portion of the side wall. The semiconductor structure extends underneath a semiconductor layer wherein a top portion of the structure contacts the semiconductor layer.

Abstract: Microelectronic systems having integrated heat dissipation posts are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the step or process of obtaining a microelectronic component from which a heat dissipation post projects. The microelectronic component is placed or seated on a substrate, such as a multilayer printed circuit board, having a socket cavity therein. The heat dissipation post is received in the socket cavity as the microelectronic component is seated on the substrate. Concurrent with or after seating the microelectronic component, the microelectronic component and the heat dissipation post are bonded to the substrate. In certain embodiments, the heat dissipation post may be dimensioned or sized such that, when the microelectronic component is seated on the substrate, the heat dissipation post occupies a volumetric majority of the socket cavity.