Abstract: A method of assembling QFP devices includes providing a lead frame having leads that extend from a dam bar to a die flag, and performing a first molding process that fills spaces between the leads and between the dam bar and the die flag with a first mold compound. The first mold compound also forms a ring around the die flag, where the ring extends from both lateral sides of the lead frame. A first area around the die flag is removed to separate the leads from the die flag, and a second area near an inner corner of the dam bar is removed to form a mold gate. A die is attached to the die flag and electrically connected to the leads with bond wires, and then a second molding process is performed to encapsulate the die, bond wires and inner leads.

Abstract: A data-clustering method generates data clusters for a set of data points. A region of interest containing the data points and a center matrix for the region of interest are defined, where the center matrix includes an array of center points defining centers of overlapping circles. The data points are mapped to corresponding circles based on near center points. Pairs of overlapping circles are merged based on relative numbers of data points lying in overlap regions of the pairs of overlapping circles compared to total numbers of data points within the corresponding circles. Circles belonging to the one or more data clusters are identified based on merged pairs of overlapping circles, and data points belonging to the one or more data clusters are identified based on the corresponding circles. The method may be performed by a computer having a heterogeneous architecture with parallel processors.

Abstract: An integrated circuit includes a security module with multiple stages arranged in a pipeline, with each stage executing a different operation for accessing stored lifecycle (LC) information. For each portion of LC being accessed, each stage performs N iterations of its corresponding operation, whereby N is an integer greater than two, and crosschecks the results of successive iterations to ensure that the results of the operation are consistent. In addition, the stages of the security module are overlapping, such that different stages can perform different iterations concurrently. These concurrent operations at different stages are organized such that they may also be crosschecked and thereby confirm “offset” results between the stages.

Abstract: A contactless communication device includes a receiver unit having differential input terminals for connecting to an antenna. The receiver unit is coupled to a transmitting device and receives an RF signal transmitted by the transmitting device. A first comparator is adapted to generate a first comparator output signal indicative of a relationship between a voltage at a positive input terminal of the receiver unit and a first reference voltage. A second comparator is adapted to generate a second comparator output signal indicative of a relationship between a voltage at a negative input terminal of the receiver unit and a second reference voltage. A first voltage regulation circuit is adapted to regulate the voltage at the positive input terminal in response to the first comparator output signal. A second voltage regulation circuit is adapted to regulate the voltage at the negative input terminal in response to the second comparator output signal.

Abstract: One example discloses a wireless network device, wherein the wireless device is a second wireless device configured to receive a set of original signal transmissions from a first wireless device; wherein the set of original signal transmissions includes a signal for the second wireless device and a signal for a third wireless device; wherein the second wireless device is configured to detect a timing interval between individual signal transmissions within the set of original signal transmissions; wherein the second wireless device is configured to re-transmit the signal for the third wireless device substantially in-phase with the timing interval.

Abstract: A system includes a rotary platform adapted to undergo oscillatory motion about a fixed point, a test fixture coupled to the rotary platform, the test fixture being adapted to receive a device-under-test, and an inertial sensor mounted to the rotary platform for providing a motion output signal indicative of the oscillatory motion. A controller is in communication with the rotary platform and inertial sensor. The controller receives the motion output signal and provides a drive signal to the rotary platform responsive to the motion output signal. The controller generates the drive signal in response a test profile and the motion output signal provides feedback of actual movement of the rotary platform. The motion output signal is input to the controller to ensure correspondence between the drive signal and the test profile. A multitude of differing validated environmental vibrational stimuli effects can be evaluated via a sense signal from the device.

Abstract: Aspects of the present disclosure are directed to processing signals received from different sources, such as may be relevant to receiving signals having respective time-offsets based upon a distance via which the respective signals travel, and/or due to an oscillator clock mismatch. As may be implemented in accordance with one or more embodiments, respective fast Fourier transform (FFT) series are generated for symbols in respective ones of communications received in parallel. For each message that the receiver is trying to decode, channel estimation is performed on the respective FFT series, and one of the FFT series is selected based upon metrics indicative of interference in the respective FFT series, for that particular message. A decoding timing window is set based on the selected FFT series, and the selected FFT series is decoded.

Abstract: A Doherty amplifier module includes first and second amplifier die. The first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal. The second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal. A phase shift and impedance inversion element is coupled between the outputs of the first and second amplifier die. A shunt inductance circuit is coupled to the output of either or both of the first and/or second amplifier die. Each shunt inductance circuit at least partially resonates out the output capacitance of the amplifier die to which it is connected to enable the electrical length of the phase shift and impedance inversion element to be increased.

Abstract: A central network component, a FlexRay-compatible central network component, and a method for bit processing in a central network component are described. In one embodiment, a central network component for facilitating communication among communication nodes includes a bit oversampling module configured to oversample bits received from a first communication node of the communication nodes with an oversampling factor to generate oversampled bit streams, a time point selection module configured to select time points in the oversampled bit streams, where the time points correspond to inner samples of the oversampled bit streams with respect to the oversampling factor, and a bit outputting module configured to output the inner samples to a second communication node of the communication nodes between the time points. Other embodiments are also described.

Abstract: An FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described. The FFT device comprises a control unit, a coefficient unit, and a transformation unit. The control unit controls a sequence of transformation rounds, the transformation rounds including two or more FFT rounds and further including or not including a window round. The control unit also maintains configuration data indicating for each of said transformation rounds whether the respective transformation round is an FFT round, a window-FFT round, or a window round. The coefficient unit provides transformation data. The transformation unit is arranged to receive the transformation data and to perform the respective linear transformation on the basis of the transformation data. A method for performing a Fast Fourier Transform is described as well.

Abstract: According to a first aspect of the present disclosure, an integrated circuit is provided which comprises an active shield in a first layer and at least one security-critical component in a second layer, said security-critical component being configured to generate an access key for enabling access to at least a part of said security-critical component, wherein said access key is based on an output value of the active shield. According to a second aspect of the present disclosure, a corresponding method for protecting an integrated circuit is conceived. According to a third aspect of the present disclosure, a corresponding computer program product is provided.

Abstract: According to a first aspect of the present disclosure, an electronic tamper detection device is provided, comprising a radio frequency antenna, a tamper loop, a power level determination unit and a tamper measurement unit, wherein: the power level determination unit is configured to determine a power level of the tamper detection device; the tamper measurement unit is configured to generate a measurement signal and to transmit said measurement signal through the tamper loop; the tamper measurement unit is further configured to adapt the measurement signal in dependence on the power level. According to a second aspect of the present disclosure, a corresponding tamper detection method is conceived. According to a third aspect of the present disclosure, a corresponding non-transitory computer-readable storage medium comprising instructions is provided.

Abstract: A load switch includes a switch element and first and second control circuits. The switch element has an input terminal for receiving an input voltage, an output terminal for providing an output voltage, and a control terminal for receiving a switch signal, which turns the switch element on and off. The first control circuit is connected to the control terminal of the switch element and turns off the switch element in response to a first control signal. The second control circuit also is connected to the control terminal of the switch element and keeps the switch element turned off, after the first control circuit has turned off the switch element.

Abstract: An embodiment of a Doherty amplifier module includes a substrate, a first amplifier die, and a second amplifier die. The first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal. The second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal. The first and second amplifier die each also include an elongated output pad that is configured to enable a pluralities of wirebonds to be connected in parallel along the length of the elongated output pad so that the pluralities of wirebonds extend in perpendicular directions to the first and second signal paths.

Abstract: A regulated charge pump circuit and method of operation are described. A charge pump is configured to supply an output voltage to a load, and includes at least one charge pump stage, a charge pump driver arranged to drive the charge pump stages and a controllable current source connected between a supply voltage and the charge pump driver. An analog regulation loop includes a measurement circuit arranged to output an analog regulation signal indicative of a difference between a current value of the output voltage and a target value of the output voltage. A signal path is connected to the charge pump to supply the analog regulation signal to the controllable current source to operate the controllable current source to modulate the supply voltage that can be provided to the charge pump driver to regulate the output voltage.

Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.

Abstract: A phase locked loop for generating a frequency chirp is disclosed. The phase locked loop comprises a phase frequency detector configured to receive a reference frequency signal at a first input, a low pass filter configured to receive a current from the phase frequency detector at a filter input, and to output a control voltage, a voltage controlled oscillator configured to generate the frequency chirp at an output in response to receiving the control voltage, a feedback path connecting the output of the voltage controlled oscillator to a second input of the phase frequency detector, the feedback path comprising a frequency divider; and a timing module configured to generate a reset pulse. The low pass filter comprises a plurality of capacitors connected in parallel between the filter input and a common voltage line; and a voltage source configured to generate an initial control voltage.

Abstract: The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable load section, which is provided for selectively exposing one of a plurality of distinct loads to a reference source connected to a reference voltage signal input of the equalization circuit, and a logic section, which is arranged to accept a state signal from the ADC and to selectively connect one distinct load out of the plurality of distinct loads in response to the state signal. The state signal is indicative of an actual operation state of the ADC.

Abstract: A circuit for correction of a signal which is susceptible to baseline wander. The circuit includes a front-end signal processing circuit, a slicer circuit, and a summing cross-over filter circuit. The front-end signal processing circuit includes a digital processing logic circuit and is used to process an input signal by mitigating signal artifacts. The slicer circuit samples the processed input signal and, therefrom, generates a symbol output derived from the sampled processed input signal. The summing cross-over filter circuit is arranged between the front-end signal processing circuit and the slicer circuit and mitigates baseline wander in the symbol output.

Abstract: An RF amplifier is described including an input, an output, a parallel arrangement of a first branch and at least one further branch, each branch comprising a bipolar transistor in a degenerative emitter configuration having a base coupled to the input, a collector coupled to a common collector node, and an emitter degeneration impedance arranged between the emitter and a common rail. The common collector node is coupled to the output, the base of the first branch bipolar transistor is biased at a first bias voltage and the base of the at least one further branch bipolar transistor is biased at a bias voltage offset from the first bias voltage. In operation of the RF amplifier a IM3 distortion current output by the first branch bipolar transistor is in antiphase to a IM3 distortion current output by the at least one further branch bipolar transistor.