Abstract: Various embodiments relate to a circuit, including: a first secure circuit configured to receive an input and to produce a first output; a first delay circuit configured to receive the first output and to produce a first delayed output delayed by a time N; a second delay circuit configured to receive the input and to produce a delayed input delayed by a time N; a second secure circuit configured to receive the delayed input and to produce a second delayed output; and a comparator configured to compare the first delayed output to the second delayed output and to produce a result, wherein the result is one of the first delayed output or second delayed output when the first delayed output matches the second delayed output and the result is an error value when the first delayed output does not match the second delayed output.

Abstract: An apparatus for detecting disconnection of a secondary side of a current transformer includes a sampling circuit coupled to the secondary side of the current transformer that samples signals from the secondary side of the current transformer. A pull-up circuit is switchably coupled to the sampling circuit in response to a coupling signal in a diagnostic phase. A processor is coupled to the sampling circuit for receiving sampled signals from the sampling circuit. The processor extracts corresponding signal information from the sampled signals and stores the extracted signal information in a memory. The extracted signal information corresponds to statuses that the secondary side of the current transformer is connected or disconnected to a load. A detector is coupled to the processor and the memory, and accesses the memory using the signal information of the sampled signals.

Abstract: A processing module for a receiver device. The processor module comprises a channel estimate generation component arranged to output channel estimate information for a received signal, and a timestamping module arranged to determine a ToA measurement for a marker within a packet of the received signal based at least partly on the channel estimate information for the received signal generated by the channel estimate generation component. The channel estimate generation component comprises a validation component arranged to derive a validation pattern for the packet within the received signal for which a ToA measurement is to be determined, identify a section of the packet containing a validation sequence, and perform cross-correlation between at least a part of the validation sequence within the packet and at least a part of the validation pattern to generate channel estimate validation information.

Abstract: A method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection includes randomizing an order of a plurality of unit elements of a DAC, wherein each of the unit elements is controlled by a respective one of a plurality of digital inputs of the DAC. The plurality of digital inputs is sequentially asserted over at least a subset of a full set of the digital inputs to generate a plurality of analog values of an output of the DAC. A first SNDR of the DAC is measured from the plurality of analog values. A maximum SNDR, corresponding to an optimal order, is determined from the first SNDR and at least one previously measured SNDR. The optimal order of the unit elements of the DAC is stored in a memory to define connections between the digital inputs and the respective unit elements based on the optimal order.

Abstract: An embodiment for operation of an emulated electrically erasable (EEE) memory system includes a memory controller configured to identify a first quick record of a stack of quick records as a present record, wherein the stack of quick records are stored in a non-volatile portion of memory, the first quick record has a quick record status identifier (ID) that indicates the stack of quick records has not been qualified, determine a record status of a next record after the present record in the non-volatile portion of memory, and in response to a determination that the next record has a blank record status ID: update the next record from the blank record status ID to the quick record status ID, wherein the blank record status ID indicates that the next record is part of the stack of quick records, and qualify the present record using the plurality of program steps.

Abstract: A signal processor comprising: a signal-manipulation-block configured to: receive a cepstrum-input-signal, wherein the cepstrum-input-signal is in the cepstrum domain and comprises a plurality of bins; receive a pitch-bin-identifier that is indicative of a pitch-bin in the cepstrum-input-signal; and generate a cepstrum-output-signal based on the cepstrum-input-signal by: scaling the pitch-bin relative to one or more of the other bins of the cepstrum-input-signal; or determining an output-pitch-bin-value based on the pitch-bin, and setting one or more of the other bins of the cepstrum-input-signal to a predefined value; or determining an output-other-bin-value based on one or more of the other bins of the cepstrum-input-signal, and setting the pitch-bin to a predefined value.

Abstract: A method includes selectively communicating each of a plurality of motor winding signals to a first node at an integrated circuit based on whether the corresponding motor winding is energized. A zero-crossing event at an unenergized motor winding signal is determined based the unenergized motor winding signal and based on a signal at the first node.

Abstract: Aspects of the present disclosure are directed to methods, apparatuses and systems involving establishing communication with wireless devices. According to an example embodiment, a system comprises orientation circuitry configured and arranged to obtain orientation data indicative of a physical orientation of the user, a communication circuit configured and arranged to wirelessly communicate data with a plurality of wireless devices, and processor circuitry. The processor circuitry is configured and arranged to: determine a direction of interest using the orientation data, select a wireless device from the plurality wireless devices based on the direction of interest, the selection being based on information indicating a location of the user relative to the plurality of wireless devices, and establish communication between the system and the selected wireless device.

Abstract: A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.

Abstract: A voltage sampling circuit and method are provided. The voltage sampling circuit includes a capacitor having a first terminal and a second terminal. A first pre-charge circuit is coupled to a first voltage supply terminal and to the first terminal of the capacitor. The first pre-charge circuit is configured to receive a first control signal and pre-charge the capacitor to a first voltage. A switch circuit includes a first transistor having a first current electrode coupled to an input terminal of the voltage sampling circuit, a control electrode coupled to the first terminal of the capacitor, and a body electrode coupled to the second terminal of the capacitor. A second transistor having a first current electrode coupled to a second current electrode of the first transistor, a body electrode coupled to the second terminal of the capacitor, and a second current electrode coupled to an output terminal of the voltage sampling circuit.

Abstract: Embodiments of a device are provided, including a semiconductor substrate including an active device area; a body region disposed in the semiconductor substrate within the active device area, wherein a channel is formed within the body region during operation; a doped isolation layer disposed in the semiconductor substrate underneath the active device area, the doped isolation layer including an opening positioned under the active device area; and a lightly-doped isolation layer disposed in the semiconductor substrate underneath the active device area, the lightly-doped isolation layer positioned at least within the opening and in electrical contact with the doped isolation layer, wherein the doped isolation layer and the lightly-doped isolation layer form a doped isolation barrier that extends across an entire lateral extent of the active device area.

Abstract: To calibrate an accelerometer, a rotating member is rotated over multiple periods, thereby causing the accelerometer attached to the rotating member to repeatedly turn over. A processor obtains acceleration measurements as the accelerometer turns and determines a set of local minima and maxima of the acceleration measurements. Based on these local minima and maxima, the processor determines a sensitivity of the accelerometer. The processor stores the sensitivity for use in adjusting subsequent accelerometer measurements, thus calibrating the accelerometer.

Abstract: A processor configured to: receive, at a floating-point-input-terminal, an input-block of data comprising a plurality of floating-point numbers each floating-point number comprising a mantissa and an exponent; determine an input-scale-factor based on a previous-input-block-exponent-value associated with a previous-input-block of data; and convert the input-block of data into a fixed-point-block of data in accordance with the input-scale-factor, wherein the fixed-point-block of data comprises a plurality of fixed-point-values that can represent the plurality of floating-point numbers within a particular range.

Abstract: An integrated circuit includes a first plurality of flip flops; a first bank of resistive memory cells, wherein each flip flop of the first plurality of flip flops uniquely corresponds to a resistive memory cell of the first bank of resistive memory cells; write circuitry configured to store data from the first plurality of flip flops to the first bank of resistive memory cells; and read circuitry configured to read data from the first bank of resistive memory cells and provide the data from the first bank for storage into the first plurality of flip flops.

Abstract: The present disclosure teaches a Field-Effect Transistor (FET) configured as a diode to provide ESD protection. The field-effect transistor has its gate, source, and body connected to a common power supply rail. A low-density doped drain region extends in a length direction beyond the gate sidewall spacers of the transistor to provide a lower leakage current than would otherwise be exhibited by the protection device.

Abstract: Microelectronic systems having embedded heat dissipation structures are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the steps or processes of obtaining a substrate having a tunnel formed therethrough, attaching a microelectronic component to a frontside of the substrate at a location covering the tunnel, and producing an embedded heat dissipation structure at least partially within the tunnel after attaching the microelectronic component to the substrate. The step of producing may include application of a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate. The bond layer precursor material may then be subjected to sintering process or otherwise cured to form a thermally-conductive component bond layer in contact with the microelectronic component.

Abstract: Embodiments include a method of adding first and second binary numbers having C bits and divided into D words to provide a third binary number in E successive adding operations, C, D and E being plural positive integers, the method comprising: a first group of D adding operations adding together respective words of the first and second binary numbers to provide D sum and carry outputs ranging from a least significant to a most significant sum and carry output; one or more subsequent groups of adding operations adding together sum and carry outputs from an immediately preceding group of adding operations, a final group of the one or more subsequent groups resulting in the third binary number consisting of the sum outputs from the final group and a carry from the most significant carry output of the final group, wherein E is less than D.

Abstract: The invention relates to a control circuit (250) for a power supply unit (200) that has an input (207, 209) for receiving a mains supply (208), the control circuit (250) configured to: sample the input (207, 209) in order to obtain a first sample value; sample the input (207, 209) in order to obtain a second sample value subsequent to obtaining the first sample value; compare the first and second sample values to provide an outcome; set a delay interval in accordance with the outcome of the comparison of the first and second sample values; and sample the input (207, 209) in order to obtain a third sample value after the delay interval has elapsed.

Abstract: Exemplary embodiments of the present disclosure are directed towards a system and methods employed for signal reception by providing programmable and switchable line terminations a universal serial bus physical layer. The system comprising at least one switching unit comprising at least two receiver pad units configured to provide programmable and switchable line terminations for signal reception in the universal serial bus physical layer. The switching unit further comprises at least one current mode logic switching unit interfaced with the receiver pad units. The system further comprises two pairs of receiver pads connected to the receiver pad units configured to receive a plurality of speed signals from at least four transmission units. The receiver pad units are enabled to route the plurality of speed signals to at least one input of a receive amplifier through the current mode logic switching unit.

Abstract: A method of assembling QFP devices includes providing a lead frame having leads that extend from a dam bar to a die flag, and performing a first molding process that fills spaces between the leads and between the dam bar and the die flag with a first mold compound. The first mold compound also forms a ring around the die flag, where the ring extends from both lateral sides of the lead frame. A first area around the die flag is removed to separate the leads from the die flag, and a second area near an inner corner of the dam bar is removed to form a mold gate. A die is attached to the die flag and electrically connected to the leads with bond wires, and then a second molding process is performed to encapsulate the die, bond wires and inner leads.