Abstract: An oscillator system for an integrated circuit includes a first oscillator circuit, a second oscillator circuit, and calibration system. During a sampling routine, the calibration system is used to determine a sampled value based on a comparison of the output of the second oscillator and an external clock signal. The sampled value is stored in a memory. During a calibration routine, the calibration system determines a comparison value based on a comparison of the output of the second oscillator circuit and the output of the first oscillator circuit. The calibration circuit compares the comparison value with the sampled value to generate a tuning value to tune the frequency of the first oscillator circuit.

Abstract: An oscillator system includes a voltage controlled oscillator (VCO) circuit. The VCO circuit includes an output for providing an oscillation signal and input to receive a voltage that controls the frequency of the oscillation signal. The oscillator system includes a frequency to voltage circuit that receives the oscillation signal and produces a voltage that is dependent upon the frequency of the oscillation signal. The oscillator system includes a comparison circuit including an amplifier. The amplifier includes an inverting input, a non inverting input, and an output. During a first phase of the comparison circuit, the non inverting input receives a reference voltage and the inverting input is coupled to the output of the amplifier via a switch and to a capacitor wherein the capacitor samples the voltage of the output.

Abstract: A lead frame strip includes an array of lead frames. The lead frames each include a die pad and lead fingers that are spaced from the die pads and disposed along one or more sides of the die pads. The lead fingers have proximal ends near to the die pad and distal ends farther from the die pad. Connection bars extend between the lead frames. The lead fingers of adjacent lead frames extend from opposing sides of the connection bars. The connection bars have first portions where the lead fingers are connected thereto, and second portions between adjacent lead finger connections to the connection bar. The second portions are etched to form a bar that extends diagonally from a first one of the adjacent lead fingers connected thereto to a second one of the adjacent lead fingers connected thereto.

Abstract: The embodiments described herein include amplifier devices that are typically used in radio frequency (RF) applications. The amplifier devices described herein use a plurality of phase shifters to provide selectable back-off power. Specifically, the amplifier devices can be implemented with phase shifters having phase shift values selected to provide a desired back-off power.

Abstract: Embodiments of methods and systems for operating a communications device that communicates via inductive coupling are described. In an embodiment, a method for operating a communications device that communicates via inductive coupling involves detecting a system condition associated with the communications device and tuning a matching network of the communications device in response to the system condition, where the matching network includes a hybrid transformer that separates a receiver of the communications device from a transmitter of the communications device. Other embodiments are also described.

Abstract: High thermal performance microelectronic modules containing sinter-bonded heat dissipation structures are provided, as are methods for the fabrication thereof. In various embodiments, the method includes the steps or processes of providing a module substrate, such as a circuit board, including a cavity having metallized sidewalls. A sinter-bonded heat dissipation structure is formed within the cavity. The sintered-bonded heat dissipation structure is formed, at least in part, by inserting a prefabricated thermally-conductive body, such as a metallic (e.g., copper) coin into the cavity. A sinter precursor material (e.g., a metal particle-containing paste) is dispensed or otherwise applied into the cavity and onto surfaces of the prefabricated thermally-conductive body before, after, or concurrent with insertion of the prefabricated thermally-conductive body.

Abstract: Embodiments of methods and systems for operating a communications device that communicates via inductive coupling are described. In an embodiment, a method for operating a communications device that communicates via inductive coupling involves adjusting a configuration of the communications device in response to a clock signal that is synchronized to a received clock signal, obtaining information that corresponds to transmission current or power generated in response to the adjusted configuration, and quantifying a detuning condition in response to the obtained information. Other embodiments are also described.

Abstract: A packaged semiconductor device includes a die attached to a die flag of a lead frame wherein the die includes a first, second, third, and fourth minor side, wherein the first and second minor sides are opposite each other and the third and fourth minor sides are opposite each other. The device includes an outer-most lead of the lead frame extending outwardly from the first minor side of the die and closest to the third minor side, wherein the outer-most lead includes a thinned region located between the die and a full thickness portion of the outer-most lead. The device includes an electrical connection between the die and the outer-most lead, and an encapsulant surrounding the die, the electrical connection, and surrounding at least a portion of an outer edge of the thinned portion of the outer-most lead such that the full thickness portion of the outer-most lead extends beyond the encapsulant.

Abstract: A data processing system includes a backup nonvolatile memory (NVM), a random access memory (RAM), and a controller. The RAM includes a plurality of partitions, each partition having a different corresponding backup frequency. The controller is configured to back up the contents of each partition of the RAM to the backup NVM in accordance with the corresponding backup frequency.

Abstract: Battery charger circuitry includes a linear regulator and a current control loop. The linear regulator provides a constant current to a battery while the battery charger circuitry is in a current control mode. While the battery charger circuitry is in a constant voltage mode, the current control loop to: determine whether a charging current provided to the battery is less than an end of charging reference current; in response to the charging current being less than the end of charging reference current, to place the battery charger circuitry into an end of charging state; in response to the battery charger circuitry be placed the end of charging state, and to start a timer; and in response to the timer expiring, to enter the battery charger circuitry into a done state to end charging of the battery.

Abstract: A method and apparatus for performing distributed computation of precoding estimates within a DAS. An RRH comprises a receiver component arranged to receive uplink signals from active user devices. The RRH further comprises a processing component arranged to perform channel estimation for each active user device m, based on the received uplink signals, to obtain channel estimates Hm,i between each active user device m and the RRH, compute intra-RRH interference precoding estimates Fm for each active user device m based on the channel estimates Hm,i, and solve interference-free conditions to obtain inter-RRH interference precoding estimates for each RRH j within the DAS.

Abstract: An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. The bypass detector includes a voltage comparator with a variable hysteresis control circuit and a calibration engine. The bypass detector detects a change in impedance in the mesh when an attacker attempts to bypass the active loop using a wire. As part of a boot-up sequence, the calibration engine runs a hysteresis sweep on the voltage comparator and stores a hysteresis sweep boot-up signature. When bypass protection is enabled, the bypass detector runs a hysteresis sweep of the voltage comparator periodically at a predetermined interval. Each sweep generates a generated signature that is compared to the stored boot-up signature. Any signature mismatch will be signaled as an impedance mismatch, or tamper. The hysteresis step size is also programmable. The calibration engine can make small changes to the boot-up signature to allow for small voltage variations.

Abstract: The disclosure relates to an antenna including a substrate and a conductor pattern on the substrate. The conductor pattern comprises first and second conductor areas and the first conductor area is generally at a first end of the substrate and the second conductor area is generally at an opposing second end of the substrate. A first direction extends between the first and second ends of the substrate. The first conductor area has two arms, the two first conductor area arms extend parallel to the first direction and define a first slot between them; wherein the second conductor area has two arms with a second slot defined between them, and the two second conductor area arms extend parallel to the first direction. The two second conductor area arms sit within the first slot with a portion of the first slot at the outer sides of the two second conductor area arms.

Abstract: An electronic control unit suitable for a motorcycle provides diagnostic support, tachometer drive and warning lamp drive all multiplexed onto one pin and driven by a single driver circuit. In a diagnostics mode, the pin is connected to diagnostic equipment. When a diagnostic test has been completed, a tachometer drive signal is output on the pin, the drive signal having a duty cycle set high enough to illuminate the warning lamp if a fault condition is detected by on-board sensors. By combining multiple functions onto a single pin with a single driver circuit, the cost of implementing an engine control unit may be reduced compared with existing arrangements which require separate pins and drivers for each function.

Abstract: A radio frequency (RF) transceiver includes a transmitter portion configured to transmit RF signals at an output of a power amplifier (PA). A receiver portion has an input coupled to the output of the PA. The receiver portion includes a switch coupled to feedback first baseband signals to the transmitter portion during a feedback mode. The first baseband signals are based on the first RF signals received at the input of the receiver portion. A pre-distortion processing unit is coupled to receive the first baseband signals. In turn, the distortion processing unit provides pre-distortion feedback signals to the transmitter portion.

Abstract: An analog-to-digital converter (ADC) includes a split-capacitor digital-to-analog converter (DAC) having a Most Significant Bits (MSBs) sub-DAC with one or more MSBs encoded with one or more binary capacitors and one or more MSBs encoded with one or more thermometer capacitors, a Least Significant Bits (LSBs) sub-DAC, a termination capacitor coupled to the LSBs sub-DAC, and a scaling capacitor coupled between the LSBs and MSBs sub-DACs, and coupled to receive an analog input voltage, a high reference voltage, and a low reference voltage, and to provide an output voltage.

Abstract: A voltage regulator includes first and second bias circuits, a transistor, and a load prediction circuit. The transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode for providing a regulated output voltage, and a control electrode. The first biasing circuit is for providing a first bias voltage to the control electrode of the transistor in response to a feedback signal generated from the regulated output voltage. The second biasing circuit is for providing a second bias voltage to the control electrode of the transistor in response to a control signal. The load current prediction circuit is coupled to the second biasing circuit. The load prediction circuit is for providing the control signal to the second biasing circuit in response to determining that a load current at the second current electrode is expected to increase.

Abstract: According to a first aspect of the present disclosure, a power switching circuit is provided, comprising: a bandgap reference circuit configured to receive an input voltage and to generate a reference voltage in response to receiving said input voltage; a supply selection circuit configured to receive at least two supply voltages, to select the highest voltage of said supply voltages and to provide said highest voltage to the bandgap reference circuit. According to a second aspect of the present disclosure, a corresponding method of operating a power switching circuit is conceived.

Abstract: The disclosure relates to an integrated circuit comprising: a first voltage terminal; a second voltage terminal; and a plurality of logic cells, comprising one or more field effect transistors having a p-type channel and one or more field effect transistors having an n-type channel. The plurality of logic cells comprises a regular subset of cells and a spare subset of cells. Electrical connectors are arranged to: connect the gates of the regular subset of cells in order to provide a functional logic arrangement; connect the gates of the one or more field effect transistors having a p-type channel of the spare subset of cells to the first voltage terminal; and connect the gates of the one or more field effect transistors having an n-type channel of the spare subset of cells to the second voltage terminal.

Abstract: Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. The memory includes a number of different memory banks, and the memory controller includes a number of different access ports coupled to the memory banks. The memory controller is also configured to provide asymmetric memory access for access requests to memory banks based upon access ports used for memory access requests. Additional disclosed embodiments further use asymmetric access times or asymmetric access bandwidths to provide this asymmetric access to memory banks within system memories for integrated circuit (IC) systems. By providing asymmetric access times or bandwidths for multiple access ports within a memory controller to multiple different memory banks within a system memory, overall access latency or system cost is reduced for the IC systems.