Abstract: A device package is formed form a volume of molding material that encapsulates a component. Edges of the component are protected by encapsulated areas formed above the edges by a filler material prior to molding the component. The molding material also encapsulates the filler material and positioning of the filler material defines a location and dimensions of an aperture in the molding material that exposes a portion of a top surface of the component.

Abstract: Power amplifier modules (PAMs) having topside cooling interfaces are disclosed, as are methods for fabricating such PAMs. In embodiments, the method includes attaching the RF power die to a die support-surface of a module substrate. The RF power die is attached to the module substrate in an inverted orientation such that a frontside of the RF power die faces the module substrate. When attaching the RF power die to the module substrate, a frontside input/output interface of the RF power die is electrically coupled to corresponding substrate interconnect features of the module substrate. The method further includes providing a primary heat extraction path extending from the transistor channel of the RF power die to a topside cooling interface of the PAM in a direction opposite the module substrate.

Abstract: Embodiments of a multi-mode transition circuit for a DC-DC converter and a DC-DC converter are disclosed. In an embodiment, a multi-mode transition circuit for a DC-DC converter includes a transconductance amplifier operably connected to a first resistor-capacitor (RC) network and switches, a comparator operably connected to a second RC network, where the first and second RC networks are operably connected to a reference voltage, a multiplexer operably connected to the transconductance amplifier and the comparator, and an operation mode selector configured to enable or disable the transconductance amplifier and turn on or off the switches in a sequence when transitioning between a pulse-frequency modulation (PFM) mode and a pulse-width modulation (PWM) mode.

Abstract: A semiconductor device and fabrication method are described for manufacturing a heterojunction bipolar transistor by forming a silicon collector region in a substrate which includes a lower collector layer, a dopant diffusion barrier layer, and an upper collector layer, where the formation of the dopant diffusion barrier layer reduces diffusion of dopants from the lower collector layer into the upper collector layer during one or more subsequent manufacturing steps which are used to form a trench isolation region in the substrate along with a heterogeneous base region and a silicon emitter region.

Abstract: A main memory includes a first plurality of input/outputs (I/Os) configured to output data stored in the main memory in response to a read access request. A first portion of the first plurality of IOs provides user read data in response to the read access request and a second portion of the first plurality of IOs provides candidate replacement IOs. Repair circuitry is configured to selectively replace one or more IOs of the first portion of IOs using one or more of the candidate replacement IOs of the second portion of IOs to provide repaired read data in response to the read access request in accordance with repair mapping information corresponding to an access address of the read access request. A static random access memory (SRAM) stores repair mapping information, and a repair cache stores cached repair mapping information from the SRAM for address locations of the main memory.

Abstract: The disclosure relates to a doppler division multiplexing (DDM) multiple input multiple output (MIMO) radar system. Example embodiments include a DDM MIMO radar system (400) comprising: a transmitter (401) connected to a plurality of transmitter antennas (4021-N) via a corresponding plurality of signal paths (4031-N) of different electrical lengths (L1-N) such that a phase of a signal transmitted by the transmitter (401) is different at each of the plurality of transmitter antennas (4021-N).

Abstract: A transmission line. The transmission line includes a reference electrode. The transmission line also includes a stripline. The stripline meanders within a plane. The stripline has a non-planar profile when viewed along a direction parallel to the plane.

Abstract: A method for determining a quality factor of a wireless charger is disclosed. The wireless charger includes an inverter, a filter, and a resonant tank circuit. The inverter receives a supply voltage and generates a PWM signal at a first node and a second node. The filter connects to the first and second nodes of the inverter to receive the PWM signal, and generates a filtered signal at a first terminal and a second terminal of a capacitor. The resonant tank circuit connects to the first and second terminals of the capacitor of the filter to receive the filtered signal, and provides wireless power at an inductor coil to a receiver. The method includes: issuing a current pulse to the resonant tank circuit; and in a Q-factor determination phase of the wireless charger, connecting the resonant tank circuit and only the capacitor of the filter in a resonance network.

Abstract: An address to perform a memory operation on a memory location in a rectangular frame buffer is received. A determination is made whether the received address identifies a memory location in a non-rectangular frame buffer corresponding to a memory location in the rectangular frame buffer. Based on the determination that the received address identifies the memory location in the non-rectangular buffer, the memory operation on the memory location in the non-rectangular buffer is performed based on the translated address. Based on the determination that the received address does not identify the memory location in the non-rectangular buffer, the memory operation in the non-rectangular frame buffer is not performed.

Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) and a comparator having a first input coupled to receive an output voltage of the DAC, a second input, and a comparison output. The ADC also includes successive-approximation-register (SAR) circuitry having an input to receive the comparison output, and an output to provide an uncalibrated digital value. The DAC includes a Most Significant Bits (MSBs) sub-DAC including a set of MSB DAC elements and a Least Significant Bits (LSBs) sub-DAC including a set of LSB DAC elements. The ADC also includes calibration circuitry which receives the uncalibrated digital value and applies one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value. The calibration circuitry obtains a calibration value for each MSB DAC element using the set of LSB DAC elements, the termination element, and at least one of the one or more redundant DAC elements.

Abstract: An inductor assembly includes a fixture element having a central core and support structures coupled to and projecting outwardly from the central core, each of the support structures having an outer edge with a notched profile of indentations extending toward the central core, and a helical inductor having multiple turns, the turns being seated in the indentations of the at least two support structures. The support structures may be equidistantly spaced apart from one another about the central core by air gaps. The inductor assembly may be incorporated in an impedance matching network, and one or more impedance matching networks may be incorporated in a defrosting system. The impedance matching network may be a single-ended network or a double-ended network.

Abstract: Various embodiments relate to a method of sounding a plurality of stations (STAs) with mixed operating bandwidths using a null data packet (NDP), wherein the bandwidth of the NDP is wider than the bandwidth of one STA, including: grouping STAs of mixed operating bandwidth in one sounding sequence by a beamformer; transmitting a null data packet announcement (NDPA) to the STAs, wherein the NDPA indicates the requested partial bandwidth channel feedback for each STA by the beamformer; transmitting the wide-bandwidth NDP to the STAs by the beamformer; transmitting beamforming report poll (BFRP) frame to the STAs to trigger uplink transmission of channel feedback reports by the beamformer; and receiving by the beamformer a partial bandwidth channel feedback within the STA's operating bandwidth from the STAs; receiving and parsing channel feedback reports from the STAs used for following steered OFDMA transmissions by the beamformer.

Abstract: An apparatus for providing an interface between a first network that operates based on a first protocol and a second network that operates based on a second protocol, includes a receive terminal configured to receive one or more first messages encoded according to the first protocol, the first messages encapsulating a plurality of second messages. The apparatus is configured to extract encapsulated second messages, determine for each of extracted second messages, and based on flow identifying information of each of extracted second messages, a flow to which the extracted second message belongs. The extracted second messages of the flow provide for transmission of the extracted second messages on the second network encoded based on the second protocol with a time spacing there between greater than a predetermined minimum time spacing.

Abstract: Methods of testing, diagnosing, or assessing the functionality of switches of an electric motor control system and/or a phase loss of an electric motor, and electric motor systems/motor control systems employing such methods, are disclosed herein. In one example embodiment, a method of diagnosing a fault includes detecting respective phase voltage signals communicated from the first, second, and third output nodes indicative of respective phase voltages occurring at the first, second, and third output nodes, respectively, and determining whether the respective phase voltages indicate that a first fault has occurred, either with respect to one or more transistors of pairs of switching transistors or with respect to one or more of first, second, and third phase windings. The determining is based upon whether the respective phase voltage signals indicate that respective phase voltages present respectively at the output nodes are equal or substantially equal to an intermediate output voltage.

Abstract: A semiconductor package comprises a lead frame, a die pad, bond pads, and leads. A die may be arranged on the die pad, the die comprising an integrated circuit. In an example, the die and at least a portion of the lead frame are encapsulated with a molding compound (MC). A first thickness of the MC over a first portion of the die is less than a second thickness over a second portion of the die to form a cavity in the MC and the MC directly contacts the first portion and the second portion of the die.

Abstract: Leadless power amplifier (PA) packages having topside termination interposer (TTI) arrangements, and associated fabrication methods, are disclosed. Embodiments of the leadless PA package include a base flange, a first set of interposer mount pads, a first RF power die, a package body. The first RF power die is attached to a die mount surface of the base flange and electrically interconnected with the first set of interposer mount pads. The TTI arrangement is electrically coupled to the first set of interposer mount pads and projects therefrom in the package height direction. The package body encloses the first RF power die and having a package topside surface opposite the lower flange surface. Topside input/output terminals of the PA package are accessible from the package topside surface and are electrically interconnected with the first RF power die through the TTI arrangement and the first set of interposer mount pads.

Abstract: An integrated circuit includes a plurality of analog inputs, and an analog multiplexer (MUX). The MUX includes a common output node configured to provide a MUX output, a plurality of analog switches, and a shared buffer. Each switch includes a corresponding bootstrap circuit coupled to a control electrode of a corresponding pass transistor in which the corresponding bootstrap circuit includes a corresponding boosting capacitor. Each analog switch of the plurality of analog switches has a first input coupled to a corresponding analog input of the plurality of analog inputs, a second input, and an output coupled to the common output node. The shared buffer has an input coupled to the common output node and coupled to provide a common buffered MUX output to the second input of each of the plurality of analog switches.

Abstract: A System-on-Chip (SoC) includes first and second voltage supply pins configured to receive first and second supply voltages, respectively, a first supply path beginning at the first supply pin, and a supply proportion checker. The first supply path includes a first plurality of voltage supply nodes and a supply switch coupled between adjacent voltage supply nodes, wherein each node is configured to provide a corresponding internal voltage supply to a corresponding portion of the SoC. The supply proportion checker is coupled to receive the corresponding internal voltage supply from each voltage supply node, and configured to determine whether a first internal voltage supply supplied by a first supply node of the first plurality of nodes has a legitimate proportion to a second internal voltage supply supplied by a second supply node of the first plurality of nodes, wherein the legitimacy is checked using only resistors which do not require trimming.

Abstract: A digital to analog converter (DAC) includes an amplifier including a buffer of the DAC, and a resistor ladder arrangement coupled to a non-inverting input terminal of the amplifier to generate a voltage based on a digital control word. The arrangement includes a first, least-significant bit, segment arranged in one of an R-2R or unit-R configuration, a second, most-significant bit, segment including one or more units each including a second-segment-resistor having a resistor terminal coupled to a respective second switch and having a second resistance, RMSB, and a third segment including one or more third-segment-resistors coupled in parallel to the non-inverting input terminal and connected to a first reference voltage terminal. M2 designates a number of bits in the digital control word for controlling the second switches, and the third segment has a total resistance, Rsp, based on M2.

Abstract: It is described a signal converter device (100) for converting a single-ended signal to a differential signal, the device (100) comprising: i) a multiplier device (110), configured to receive a single-ended incoming signal (105), and multiply the incoming signal (105) to provide a multiplied signal (115); and ii) a divider device (120), configured to receive the multiplied signal (115), and divide the multiplied signal (115) to provide a differential signal (125a, 125b). Further, a corresponding signal conversion method is described.