Patents Assigned to NXP
  • Patent number: 10209762
    Abstract: A layered network (10; 11; 12) to provide offload of data in a communication processor (100; 110; 120). The layered network (10; 11; 12) includes a first set (S1) of network elements at a first layer (L1) and a second set (S2) of one or more network elements at a second layer (L2). The network elements of the first set (S1) are configured for processing incoming data and the network elements of the second set (S2) of one or more network elements at the second layer (L2) are configured to process intermediate data received from the first set (S1) of network elements. The network elements of a particular subset (Si1) of the network elements of the first set (Si1) of network elements are connected to only a particular network element (Ei2) of the second set (S2) to transfer the incoming data processed by the network elements of the particular subset (Si1) to the particular network element (Ei2) of the second set (S2).
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Eran Glickman, Ron Bar, Benny Michalovich
  • Patent number: 10211840
    Abstract: A charge pump driver circuit comprises an output stage and a current generator component. The output stage is arranged to receive at an input node thereof a control current signal and comprises a resistance network coupled between the input node thereof and a reference voltage node and arranged to provide a resistive path through which the control current signal flows. The output stage is arranged to generate at an output node thereof a charge pump control voltage signal based on the voltage level at the input node thereof. The current generator component is arranged to receive an indication of a voltage level of a charge pump output signal, and to generate a feedback current dependent on the voltage level of the output signal, wherein the feedback current is injected into the resistive path of the resistance network through which the control current signal flows.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Pierre Pascal Savary, Dominique Delbecq, Birama Goumballa
  • Patent number: 10209345
    Abstract: A signal processing unit and a method for searching for peaks in a two-dimensional matrix of numbers are described. The matrix is analyzed row by row and then column by column. Analyzing a row comprises, for each element of the row, tagging the element in response to determining that the element is a local maximum of the row Analyzing a column comprises determining a bit field associated with the column by determining, for each element of the column, a corresponding bit field element Determining the bit field element comprises: if the element of the column has not been tagged, setting the bit field element to a predefined first value, and, if the element of the column has been tagged, determining whether the element is a local maximum and, in this case, setting the bit field element to a predefined second value different from the first value and, otherwise, setting the bit field element to the first value.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Maik Brett, Deboleena Sakalley, Rohit Tomar
  • Publication number: 20190051571
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Applicant: NXP USA, INC.
    Inventors: AUDEL SANCHEZ, LAKSHMINARAYAN VISWANATHAN, FERNANDO A. SANTOS, JAYNAL A. MOLLA
  • Publication number: 20190052228
    Abstract: A source follower method, system, and apparatus provide rail-to-rail capability to an output voltage terminal of a voltage follower feedback biased CMOS output circuit by providing a control circuit which includes first and second bypass transistors that are connected in parallel between first and second control circuit input/output terminals and controlled, respectively, by first and second control circuit inputs, and which also includes first and second current sources for injecting source and sink currents in the output node as a function, respectively, of a first bypass current through the first bypass transistor which turns ON when the output voltage rises above a top threshold voltage level and of a second bypass current through the second bypass transistor which turns ON when the output voltage falls below a bottom threshold voltage level.
    Type: Application
    Filed: August 11, 2017
    Publication date: February 14, 2019
    Applicant: NXP USA, Inc.
    Inventors: Pedro B. Zanetta, Ricardo P. Coimbra
  • Patent number: 10204229
    Abstract: A data processing system having rich execution environment (REE) and a trusted execution environment (TEE) is provided. In the data processing system, an unsecure memory is coupled to the REE and used for storing encrypted data for use in the TEE. The TEE may have a cache for storing the encrypted data after it is decrypted. The data in both the memory and the cache is organized in blocks, and the cache is smaller than the memory. An interpreter is provided in the TEE, along with a service block in the REE, for fetching and decrypting the data to be stored in the cache. The interpreter checks an integrity of the decrypted data using a hash tree having multiple levels. In the event of a cache miss, all blocks of the hash tree in a path from the data block to a root block are retrieved from the memory in one access operation. A method for operating the cache in the data processing system is also provided.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: February 12, 2019
    Assignee: NXP B.V.
    Inventors: Jan Hoogerbrugge, Wilhelmus Petrus Adrianus Johannus Michiels, Joppe Willem Bos
  • Patent number: 10205423
    Abstract: A source follower method, system, and apparatus provide rail-to-rail capability to an output voltage terminal of a voltage follower feedback biased CMOS output circuit by providing a control circuit which includes first and second bypass transistors that are connected in parallel between first and second control circuit input/output terminals and controlled, respectively, by first and second control circuit inputs, and which also includes first and second current sources for injecting source and sink currents in the output node as a function, respectively, of a first bypass current through the first bypass transistor which turns ON when the output voltage rises above a top threshold voltage level and of a second bypass current through the second bypass transistor which turns ON when the output voltage falls below a bottom threshold voltage level.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: February 12, 2019
    Assignee: NXP USA, Inc.
    Inventors: Pedro B. Zanetta, Ricardo P. Coimbra
  • Patent number: 10205441
    Abstract: A level shifter includes a level shifting circuit, a variable bias voltage generator, and a bias voltage generator controller. The level shifting circuit is configured to level shift an input signal at a first voltage level to an output signal having a second voltage level. The second voltage level is higher than the first voltage level. The level shifting circuit includes a current mirror, an input circuit for receiving the differential input signals, and a coupling circuit for coupling the current mirror to the input circuit in response to a variable bias voltage. The variable bias voltage generator is configured to provide the variable bias voltage at one of a plurality of voltage levels. The bias voltage generator controller provides a select signal to select the voltage level from the plurality of voltage levels in response to measuring the duty cycle of the output signal to maintain the duty cycle of the output signal at a predetermined duty cycle.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 12, 2019
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Srikanth Jagannathan
  • Patent number: 10204860
    Abstract: A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least one major surface of the first metal layer, and forming a second dielectric layer over the first metal layer and the first graphene layer. The method further includes forming an opening in the second dielectric layer which exposes the first metal layer, forming a second metal layer over the second dielectric layer and within the opening, and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: February 12, 2019
    Assignee: NXP USA, Inc.
    Inventors: Douglas M. Reber, Mehul D. Shroff
  • Publication number: 20190043774
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 7, 2019
    Applicant: NXP USA, INC.
    Inventors: AUDEL SANCHEZ, LAKSHMINARAYAN VISWANATHAN, FERNANDO A. SANTOS, JAYNAL A. MOLLA
  • Publication number: 20190043775
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 7, 2019
    Applicant: NXP USA, INC.
    Inventors: AUDEL SANCHEZ, LAKSHMINARAYAN VISWANATHAN, FERNANDO A. SANTOS, JAYNAL A. MOLLA
  • Patent number: 10198110
    Abstract: It is disclosed a touch sensor (100,200,300,400,500,700) for sensing a user touch, comprising an electrically conductive structure (101) having an electrically conductive touch area (103) exposed to the environment; a first capacitor (115) having a first electrode (117) electrically connected with the conductive structure (101); a second capacitor (119) having a first electrode (121) connected to a second electrode (123) of the first capacitor (115); and a driver arrangement (125) connected to the first capacitor and the second capacitor and adapted to perform particular operation steps.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: February 5, 2019
    Assignee: NXP B.V.
    Inventors: Thomas Suwald, Arne Burghardt
  • Patent number: 10198062
    Abstract: Various exemplary embodiments relate to an event-driven processing unit (EPU) and a related method. A microprocessor may halt processing instructions when it executes a halting command. Thereafter, an EPU clock may stop its processing cycle and therefore halt microprocessor execution until it receives a start signal by a pattern detector. The pattern detector may use a plurality of bit slices to monitor a plurality of external inputs for the occurrence of events specified by the user. Some embodiments may also allow the user to check functioning by skipping upcoming instructions if a monitored event did not occur. By halting the EPU clock and the execution flow of the microprocessor, the event-driven microprocessor minimizes waste associated with executing a main control loop while waiting for a monitored event to occur. This may save processing capacity, memory, and power associated with continually running the main control loop.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: February 5, 2019
    Assignee: NXP B.V.
    Inventors: Adam Fuks, Rob Cosaro
  • Patent number: 10200431
    Abstract: A multimedia system includes a source device for providing a media stream and a sink device for playing the media stream. The source device encapsulates the media stream into data packets with corresponding timestamps associated with a first wall time, and transmits the data packets to the sink device based on the timestamps and the first wall time. The sink device provides a second wall time based on the second global clock, synchronizes the second wall time with the first wall time through a network protocol, generates a local media clock, and locks the local media clock to the second global clock. The sink device decapsulates the data packets, and then plays the media stream with the locked local media clock. A play-out time of each data packet is determined by a corresponding timestamp and the second wall time.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: February 5, 2019
    Assignee: NXP USA, Inc.
    Inventors: Luwei Zhou, Zhi Li
  • Patent number: 10200091
    Abstract: A device for inductively coupled communications includes an NFC module for generating an electromagnetic carrier signal and modulating the carrier signal according to data to be transmitted, and an antenna circuit coupled to and driven by said NFC module with the modulated carrier signal. The device includes an RF front end coupled between said NFC module and said antenna circuit. The RF front end includes a balanced to unbalanced (Balun) transformer and a tuning capacitor. The Balun transformer has a first winding coupled to said NFC module via differential transmitter terminals of said NFC module and a second winding coupled to said tuning capacitor. A first terminal of said tuning capacitor is coupled to a receiving terminal of said NFC module. The Balun transformer and tuning capacitor provide a function of an electromagnetic compatibility (EMC) filter.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: February 5, 2019
    Assignee: NXP B.V.
    Inventors: Jingfeng Ding, Gernot Hueber, Ian Thomas Macnamara
  • Patent number: 10199477
    Abstract: An embodiment of a complementary GaN integrated circuit includes a GaN layer with a first bandgap. A second layer with a second bandgap is formed on the GaN layer, resulting in a 2DEG in a contact region between the GaN layer and the second layer. The second layer has a relatively thin portion and a relatively thick portion. A third layer is formed over the relatively thick portion of the second layer. The third layer has a third bandgap that is different from the second bandgap, resulting in a 2DHG in a contact region between the second layer and the third layer. A transistor of a first conductivity type includes the 2DHG, the relatively thick portion of the second layer, and the third layer, and a transistor of a second conductivity type includes the 2DEG and the relatively thin portion of the second layer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 5, 2019
    Assignee: NXP USA, INC.
    Inventor: Philippe Renaud
  • Patent number: 10199991
    Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: February 5, 2019
    Assignee: NXP USA, INC.
    Inventors: Hussain H. Ladhani, Gerard J. Bouisse, Jeffrey K. Jones
  • Patent number: 10199339
    Abstract: A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: February 5, 2019
    Assignee: NXP USA, Inc.
    Inventors: Sheila F. Chopin, Min Ding, Varughese Mathew, Scott S. Roth
  • Patent number: 10199303
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 5, 2019
    Assignee: NXP USA, INC.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos, Jaynal A. Molla
  • Patent number: 10199302
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 5, 2019
    Assignee: NXP USA, INC.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos, Jaynal A. Molla