Abstract: Embodiments of an interface system for interfacing between an NFC controller and a secure element are disclosed. In one embodiment, an interface system includes an interface memory, an interface controller, an NFC controller interface configured to exchange data between the interface system and an NFC controller, and a secure element interface configured to exchange data between the interface system and a secure element.

Abstract: A wafer-level chip-scale package (WLCSP) includes an integrated circuit (IC) chip, and die bonding pads with a redistribution layer (RDL) having multiple via structures located directly below the footprint of a solder ball placed on the bonding pad. The via structures electrically connect the solder ball to a top metal layer of the IC chip. The RDL may extend beyond the solder ball's footprint and have additional vias that connect to the top metal layer, including vias located under and connected to other solder balls. The bonding pads have a low R-on resistance and are not susceptible to thermal-induced cracking.

Abstract: A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.

Abstract: Method to extract timing diagrams from synchronized single- or two-photon pulsed LADA by spatially positioning the incident laser beam on circuit feature of interest, temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. A Single-Photon Laser-Assisted Device Alteration apparatus applies picosecond laser pulses of wavelength having photon energy equal to or greater than the silicon band-gap. A Two-Photon Laser-Assisted Device Alteration apparatus applies femtosecond laser pulses of wavelength having photon energy equal to or greater than half the silicon band-gap at the area of interest. The laser pulses are synchronized with test vectors so that pass/fail ratios can be altered using either the single-photon or the two-photon absorption effect. A sequence of synthetic images with error data illustrates timing sensitive locations.

Abstract: An integrated circuit and a method of self-testing the integrated circuit are provided. The method comprises: generating a reference voltage at an output of a reference circuit; initiating a test of the reference circuit during a test mode; determining whether the test of the reference circuit passes; and comparing, if the test of the reference circuit passes, a first voltage with the reference voltage. The disclosed test method provides for more complete testing of the integrated circuit.

Abstract: A method, system, and apparatus are provided for debugging a compiled computer program having one or more variables by generating variable location information for a first variable stored in a CPU register that is parsed from runtime disassembly information for the compiled computer program and used to generate a pattern to search for the first variable in the runtime disassembly information to identify a program address for the first variable that can be used to set a software program watchpoint for the first variable.

Abstract: A time to digital converter may include a synchronization block configured to output a voltage pulse with duration based on a time difference between a reference oscillating signal and an input oscillating signal; a charge pump arranged to receive the voltage pulse and to convert the voltage pulse into a current pulse; an integrator comprising an integrator capacitor, the integrator being configured to receive the current pulse and integrate the current pulse as a charge on the integrator capacitor, resulting in an integrator output voltage; and a successive approximation register configured to determine the integrator output voltage with respect to a reference voltage by adjusting the charge on the integrator capacitor so as to reduce the integrator output voltage to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage as a digital signal.

Abstract: A control system (100) for controlling a power consumption of an electronic device (300) is provided. The electronic device is adapted to communicate with a reader device via a wireless communication interface. The control system comprises a measuring unit (102) being adapted for measuring an actual field strength of an electromagnetic field provided by the reader device to the control system, a power delivery unit (101) being adapted for delivering power received via the electromagnetic field to the electronic device, and a control unit (103) being coupled to the measuring unit and being adapted for providing a control signal to the electronic device for controlling the consumption of the power being delivered to the electronic device, wherein the control signal is based on the actual field strength of the electromagnetic field.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.

Abstract: A phase locked loop is disclosed comprising: a phase detector, a loop filter, a frequency controller oscillator and a lock detector. The phase detector is operable in a bang-bang mode to provide a binary phase error signal indicating whether there is a positive or negative phase difference between a reference signal and a feedback signal. The loop filter is configured to provide a control signal derived from the binary phase error signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The lock/unlock detector is configured to determine a lock/unlock state of the phase locked loop, the lock/unlock state derived from a duty cycle and/or spectral content of the binary phase error signal.

Abstract: Methods for producing high thermal performance microelectronic modules containing sinter-bonded heat dissipation structures. In one embodiment, the method includes embedding a sinter-bonded heat dissipation structure in a module substrate. The step of embedding may entail applying a sinter precursor material containing metal particles into a cavity provided in the module substrate, and subsequently sintering the sinter precursor material at a maximum processing temperature less than a melt point of the metal particles to produce a sintered metal body bonded to the module substrate. A microelectronic device and a heatsink are then attached to the module substrate before, after, or concurrent with sintering such that the heatsink is thermally coupled to the microelectronic device through the sinter-bonded heat dissipation structure. In certain embodiments, the microelectronic device may be bonded to the module substrate at a location overlying the thermally-conductive structure.

Abstract: A processing device includes a target processor instruction memory to store a plurality of memory access instructions, and a compiler. A vector invariant candidate detection module of the compiler to determine whether the memory access instruction is to be replaced by vector invariant access code, and in response: the complier to generate first replacement code that vectorizes the memory access instruction using vector invariant access code, and to replace the memory access instruction with the first replacement code. A vector modulo addressing candidate detection module of the compiler to determine whether the memory access instruction is to be replaced by vector modulo addressing access code, and in response: the complier to generate second replacement code that vectorizes the memory access instruction using vector modulo addressing code, and to replace the memory access instruction with the second replacement code.

Abstract: There is described an RF communication device, the device comprising (a) a data memory for storing data, (b) an RF interface (112) for RF communication with an external RF device (130), (c) a host interface (111) for communication with a host device (120), (d) a host access memory unit (214, 215) comprising host interface access control data, the host interface access control data defining host access rules for accessing data in the data memory through the host interface (111), and (e) a host access control unit for, based on the host interface access control data, controlling access to data in the data memory through the host interface (111). There is also described a system and a method.

Abstract: A single-inductor DC-DC converter generates two DC output voltages at two capacitors. The converter selectively transfers energy from a battery to the inductor or from the inductor to a selected capacitor. While the converter is still settling, the converter is regulated based on only the more deficient DC output voltage. After the converter has already settled, the converter is regulated based on the common-mode voltage for both DC output voltages. By regulating the still-settling converter based on only the more deficient DC output voltage, instead of the common-mode voltage, even greater deficiencies in that already more-deficient DC output voltage are avoided.

Abstract: An integrated circuit (IC) having multiple cores controls write access to its input/output (I/O) pins. The IC includes a pin-control circuit, a memory, and a set of I/O pins. The pin-control circuit allows a core to independently control individual ones of the I/O pins. A set of pin-control values are defined that correspond to the set of I/O pins to indicate a type of core that can access an I/O pin. The pin-control circuit receives the pin-control values, a source ID, and write data generated by a core, and updates a pin data bit stored in the memory with a corresponding bit of the write data when the core is allowed to access the I/O pin. The pin-control circuit does not change the pin data bit when the core is denied write access to the I/O pin.

Abstract: Embodiments of a method and a system controlling an amplifier of a communications device are disclosed. In an embodiment, a method for controlling an amplifier of a communications device involves checking for a data reception at the communications device and freezing a gain of the amplifier if the data reception is detected.

Abstract: A lead frame for a packaged integrated circuit (IC) device has alternating first and second leads that protrude from a package body in respective first and second planes, where the second plane is parallel to and below the first plane. The first leads are formed into Gull Wing shaped leads and the second leads are formed into J-shaped leads. Inner lead portions of the first and second leads are maintained in the first plane with a tape. An inner lead portion of each of the second leads includes a deformation area that facilitates maintaining the tape in contact with the inner lead area of the second leads, even when a mold tool presses down on an outer lead side of the second leads to place the outer lead ends of the second leads in the second plane.

Abstract: A control circuit provides a signal to a control terminal of the transistor to control the conductivity of the transistor. The control circuit includes a voltage-to-current converter that provides an indication of the control terminal-to-current terminal voltage of a transistor. The control circuit includes control circuitry that uses the indication from the voltage-to-current converter in controlling the current applied to the control terminal.

Abstract: A bidirectional voltage translator shifts a voltage level of a first voltage signal to generate a second voltage signal, and vice-versa. The voltage translator includes first and second I/O terminals for receiving and outputting the first and second voltage signals, respectively, and first and second one-shot circuits connected to first and second output transistors, respectively. The outputs of the transistors are connected to the first and second I/O terminals, respectively, and also are fed back to the respective one-shot circuits. When the output of the voltage translator has a high slew-rate, the one of the first and second one-shot circuits that corresponds to the output modulates the gate voltage of the corresponding output transistor based on the feedback signal to control the slew-rate of the output.

Abstract: An LED driver design has a single controller used to drive multiple strings of LEDs. In one aspect there is dynamic threshold voltage setting so that the individual characteristics of the LED strings can be taken into account in the voltage control loop. In another aspect, excess energy is dissipated off-chip in a dedicated heat dissipater, and the routing of current to the heat dissipater is controlled dynamically such that a desired integrated circuit biasing remains stable.