Abstract: A safety system comprising: a safety apparatus adapted to be mounted at the rear of a bicycle and comprising a processor, a motion sensor, a threat sensing device and a user alert device, all coupled to the processor, wherein the processor is adapted to: control the driver alert device based on a threat position value and/or the threat speed value; control the user alert device based on at least one of a motion-based value, an ambient light-based value, the threat position value and the threat speed value. It is also claimed the safety apparatus and a collaborative safety system comprising a plurality of safety systems, each being coupled to a communication device through which the processor is further adapted to control the driver alert device and/or the user alert device of the others of the plurality in response to the sensing of a threat.

Abstract: Techniques for providing generation of a microplasma around a semiconductor device die or package through the use of an anode-cathode geometry that allows for microplasmas to be created at low voltage. The geometry and cathode materials cause the cathode to emit electrons through field emission. These field emission electrons result in significantly more electrons available for the generation of the microplasma than would be present due to the ambient fluid alone. Thus, the ignition and maintenance of the microplasma occurs at a lower voltage than typical for a fluid at that pressure and the distances involved.

Abstract: A method, system, and apparatus are provided for computing soft bits in a non-linear MIMO detector which decodes a signal received at a plurality of receive antennas using channel estimate information and a decoding tree to produce output data for a bit estimation value which includes a maximum likelihood solution along with a naturally ordered vector identifying all explored node metrics and node indices, where soft bits are computed for each bit estimation value by determining a set of bit-masks through repetition and indexing operations applied on the explored node indices, masking the naturally ordered vector with the set of bit-masks to generate masked node metrics, determining candidate soft bit values by subtracting metrics of all nodes that form the maximum likelihood solution from the masked node metrics, and determining a final soft bit value by identifying which of the candidate soft bit values has a lowest value.

Abstract: A method facilitates simulating a plurality of circuit elements connected to a multiport interconnect structure having a first set of ports. The method includes: receiving a first set of data that models electrical behavior of the first set of ports and a first portion of the plurality of circuit elements; determining a first subset of the first data, which models electrical behavior of a set of exposed ports of the first set of ports, and a second subset of the first data, which models electrical behavior of a set of non-exposed ports of the first set of ports and the first portion of the plurality of circuit elements; and combining the second subset of the first data into the first subset of the first data to generate a second set of data that models electrical behavior of a second interconnect structure having fewer ports than the multiport interconnect structure.

Abstract: A method of performing compression of image data for at least one image is described. The method comprises receiving image data of at least a part of the at least one image, encoding the received image data into at least one compressed data block, applying at least one bandwidth limit to the at least one compressed data block, and outputting the at least one bandwidth limited compressed data block to a buffer. The method further comprises dynamically updating the at least one bandwidth limit applied to the at least one compressed data block base at least partly on a fill level of the buffer.

Abstract: An integrated circuit optical die test interface and associated testing method are described for using scribe area optical mirror structures (106) to perform wafer die tests on MEMS optical beam waveguide (112) and optical circuit elements (113) by perpendicularly deflecting optical test signals (122) from the scribe area optical mirror structures (106) into and out of the plane of the integrated circuit die under test (104) and/or production test die (157).

Abstract: An integrated circuit includes on-chip flash memory, a EEPROM, cache memory, and a repair controller. When a defective address is detected in the flash memory, data slotted to be stored at the defective address is stored in the EEPROM by the repair controller. The cache memory includes a content addressable memory (CAM) that checks read addresses with the defective memory address and if there is a match, the data stored in the EEPROM is moved to the cache so that it can be output in place of data stored at the defective location of the flash memory. The memory repair system does not require any fuses nor is the flash required to include redundant rows or columns. Further, defective addresses can be detected and repaired on-the-fly.

Abstract: The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analog signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analog signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.

Abstract: A method of detecting overcurrent events within at least one electronic device, and an overcurrent detection module therefor. The method comprises receiving at least one current requirement indication from at least one electronic device, determining at least one overcurrent value based at least partly on the received at least one current requirement indication, receiving at least one indication of at least one input current flow for the at least one electronic device, and determining that an overcurrent event is occurring if the indicated at least one input current flow for the at least one electronic device exceeds the determined at least one overcurrent value.

Abstract: A gate drive circuit includes a first switch electrically coupled to a single-supply input voltage node, the first switch electrically coupling the voltage node with a first capacitor if switched on; a second switch electrically coupled to a ground node, the second switch electrically coupling the first capacitor with the ground node if switched on; and the first capacitor. A first capacitor lead of the first capacitor is electrically coupled to the first and second switches and a second capacitor lead of the first capacitor is arranged to connect with a power transistor gate.

Abstract: A system for use in nodes communicating over a CPRI (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management HDLC (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. Received HDLC packets can be extracted for use by a local node. Locally generated packets can be inserted into the packet data stream at the datalink layer for onward transmission over the CPRI. The system arbitrates between the locally generated packet data held in a buffer in the local node and remote packet data received from a remote node and held in the local node in a first in first out buffer for onward transmission to a subsequent node after arbitration. Remote packet data is given priority.

Abstract: A radio frequency transmission structure couples a RF signal between a first and a second radiating elements arranged at a first and a second sides of a first dielectric substrate, respectively. The RF coupling structure comprises first and second coupling structures. Each coupling structure has a hole arranged through the first dielectric substrate, a first electrically conductive layer arranged on a first wall of the hole to electrically connect a first and a second signal terminals, a second electrically conductive layer arranged on a second wall of the hole opposite to the first wall to electrically connect a first and a second reference terminals. The first electrically conductive layer is separated from the second electrically conductive layer. The first and second coupling structures are symmetrically arranged with the first electrically conductive layers closer to each other than the second electrically conductive layers are to each other.

Abstract: A memory includes a global reference circuit for generating a signal that controls the resistance of a plurality of reference devices used to read data in memory cells by sense amplifiers of the memory. The signal is generated by an output of an operational amplifier of the global reference circuit. The operational amplifier includes a first input whose voltage is set by flowing current through a reference circuit and a second input whose voltage is set by flowing current through a master reference device. The signal controls the resistance of the master reference device such that the voltages of the inputs of the operational amplifier match.

Abstract: An execution flow protection module (30) for a microcontroller (10) with a memory (24) and a microprocessor (20) is described. The module (30) is configured to monitor the memory (24) access of the microcontroller (10) to identify instructions fetched by the microcontroller (10) from the memory (24) for execution by the microprocessor (20). The module (30) comprises an instruction decoder unit (32) for determining a program counter value associated with the execution flow of the instructions fetched by the microcontroller (10); a program counter predictor unit (34) for predicting the program counter value of the next fetched instruction; and an interrupt module (40) for responding if the next instruction fetched by the microcontroller does not match the predicted program counter value.

Abstract: An RFID tag is attached to or embedded in an object and used for determining the position of the object. The RFID tag includes a controller and an energy harvester coupled to the controller. The controller provides object position information to a host device by sending ping signals to the host device. The energy harvester harvests RF energy from WLANs, converts the RF energy to DC power, and supplies the DC power to the RFID tag.

Abstract: A method of mapping an input message to an output message by a keyed cryptographic encryption operation, wherein the keyed cryptographic encryption operation includes a first round, including: performing a substitution function on a first portion of the input message to produce an output, wherein the substitution function incorporates a portion of a cryptographic key; and performing a watermarking function on the output, wherein the watermarking function produces a watermark output when the first input portion has a specific predetermined value, wherein the watermark output uniquely identifies the keyed cryptographic encryption operation.

Abstract: In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.

Abstract: A digital up-converter (DUC) includes a cascaded combinator-differentiator (CCD) filter, a low-pass filter, an up-sampler, and a down-sampler. The combinator includes a number of series-connected combinator stages and the differentiator includes a number of series-connected differentiator stages. The CCD filter functions similarly to an interpolator filter, filtering and up-sampling the baseband signal out of the baseband. In one embodiment, the up-sampling factor is twice the number of channels (2N). The disclosed DUC does not require complex mixers or oscillators. Also, the low-pass filter of the DUC does not require a narrow transition band, so the number of coefficients for the low-pass filter is relatively low.

Abstract: A semiconductor device includes an array of memory cells, and a reference voltage generation circuit including a first set of reference memory cells coupled to a first bit line, a second set of reference memory cells coupled to a second bit line, a first capacitor having a first terminal coupled to the first bit line, and a second terminal, a second capacitor having a first terminal coupled to the second terminal of the first capacitor at a first node and a second terminal coupled to the second bit line, an amplifier including a first input selectively coupled to the first node and a second input coupled to an output of the amplifier that provides reference voltage used by sense amplifiers, and a third capacitor including a first terminal coupled to the output of the amplifier and a second terminal coupled to a first supply voltage.

Abstract: According to an aspect of the invention a localization method for localizing a host device (100) in a control system, in particular a building control system, is provided, the localization method comprising determining geographical location information of the host device (100) by means of a localization device (102) and associating the geographical location information with a unique identifier of the host device (100). According to another aspect of the invention a computer program product is provided that comprises program instructions which, when being executed by one or more processing units, cause said processing units to carry out or control the steps of the inventive localization method. According to another aspect of the invention, a localization device (102), in particular a portable localization device is provided for use in the inventive localization method.