Abstract: An electronic slave device that provides one or more services to master devices, can be registered with a single true-owner device and one or more co-owner devices. The true-owner device can set independent permissions for the slave device's services as being free (all can use), restricted (only true-owner and co-owners can use), or locked (only true-owner can use), and hide locked services from non-owner devices. In one commerce mode, the slave device is sold with the true-owner device. In another commerce mode, the slave device is sold separately and the initially requesting master device can be the true-owner device.

Abstract: Embodiments of a multi-stage clock generator architecture that generates multiple non-overlapping clock phase signals includes: a first stage clock generator configured to: divide an input clock signal into a number of clock signals, synchronize each clock signal to a transition edge of a synchronization signal to produce synchronized clock signals, wherein the synchronization signal is a delayed version of the input clock signal by at least an amount sufficient to ensure that each of the clock signals become stable in response to a transition edge of the input clock signal, and generate a number of clock phase signals based on the synchronized clock signals. The architecture also includes a later stage clock generator configured to: generate a set of mutually non-overlapping clock phase signals based on the input clock signal.

Abstract: A method, reception device and host device are provided for aligning data streams at a multi-source receiver. Portions of data for a plurality of data streams are received at a reception device, the plurality of data streams carrying respective content, wherein the content of each data stream is misaligned with at least one other data stream with respect to time. The portions of data are forwarded to a host device to be stored in respective delay buffers. Indexing information is maintained for each of the delay buffers. The portions of data are forwarded to the host device along with the indexing information.

Abstract: A method performed by a radio equipment control (REC) device, including storing values of link configuration registers of a radio equipment control (REC) device at shadow registers of the REC device in response to determining that a synchronization of a current communication link between the REC device and a radio equipment (RE) device has been lost. The method further including re-establishing the current communication link based on the values of the link configuration registers stored at the shadow registers of the REC device.

Abstract: Magnetoresistive sensors are commonly used for angular detection in many automotive applications. According to an exemplary embodiment of the present invention, a sensor is provided in which a first half-bridge has magnetoresistive resistors with barber-pole stripes and in which a second half-bridge has magnetoresistive resistors without barber-pole stripes. One of the resistors without barber-pole stripes is rotated with respect to the other three resistors by 90°. This may provide for an improved angle determination with reduced angular errors due to offset.

Abstract: An apparatus and method are provided. A first buffer is configured to store a first packet stream, the first buffer comprising a first read pointer pointing to a first position in the first packet stream. A second buffer is configured to store a second packet stream. The second packet stream corresponds to the first packet stream and the second buffer comprises a second read pointer. A controller is configured to determine a second position in the second packet stream that corresponds to the first position in the first packet stream and adjust the second read pointer to point to the second position.

Abstract: A switching amplifier circuit (50) connected to drive an impedance-based antenna drive circuit (55) includes high side and low side switches (51-54) configured and connected to connect different reference voltages to first and second output nodes (ANTP, ANTN) in response to gating control signals during an active phase and a disabled phase, and also includes an output drive circuit (59) that provides a ramped output voltage drive signal to the first output node while the second output node is connected over the second low side electronic switch to the second reference voltage during a transition phase of operation between the disabled phase and active phase, where the ramped output voltage drive signal is characterized by a predetermined slew-rate between the second reference voltage and the first reference voltage over a specified time interval.

Abstract: A LVDS device, comprising: a first pair of switches, operable to drive current from a first output to a second output through a differential signalling circuit; a second pair of switches, operable to drive current from the second output to the first output through the differential signalling circuit; a voltage limiter, connected in series with the first and second pair of switches, operable to receive a control voltage and, responsive to the control voltage, to limit a voltage at each of the first and second output to less than a clamping voltage when current is driven through the differential signalling circuit.

Abstract: The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at least one an alternate bus master unit. The CPU, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. The cache invalidation unit generates one or more invalidation requests to the cache memory in response to the alternate bus master unit writing data to the main memory. The cache invalidation unit comprises a page address generator unit to generate page addresses relating to at least one address range and an invalidation request generator unit to generate an invalidation request for each page address. The one or more generated invalidation requests are transmitted by the cache invalidation unit via to the cache memory of the CPU.

Abstract: Embodiments of a transistor control device for controlling a bi-directional power transistor are disclosed. In an embodiment, a transistor control device for controlling a bi-directional power transistor includes a resistor connectable to a body terminal of the bi-directional power transistor and a transistor body switch circuit connectable to the resistor, to a drain terminal of the bi-directional power transistor, and to a source terminal of the bi-directional power transistor. The transistor body switch circuit includes switch devices and alternating current (AC) capacitive voltage dividers connected to control terminals of the switch devices. The AC capacitive voltage dividers are configured to control the switch devices to switch a voltage of the body terminal of the bi-directional power transistor as a function of a voltage between the drain terminal of the bi-directional power transistor and the source terminal of the bi-directional power transistor.

Abstract: An embodiment of a Doherty amplifier includes first and second amplifier paths with first and second amplifiers, respectively, a power divider, a series delay element, and a short-circuited stub. The power divider is configured to receive a radio frequency (RF) signal and to divide the RF signal into first and second input signals that are produced at first and second power divider outputs. The series delay element is coupled between the first power divider output and the first amplifier. The short-circuited stub is coupled between the first power divider output and the first amplifier or between the second power divider output and the second amplifier. The first amplifier path is characterized by a first frequency-dependent insertion phase, the second amplifier path is characterized by a second frequency-dependent insertion phase, and a slope of the first or second frequency-dependent insertion phase is altered by the short-circuited stub.

Abstract: A bipolar junction transistor is configured to provide electrostatic discharge (ESD) protection for an integrated circuit. The bipolar junction transistor includes a substrate configured to function as a gate for the bipolar junction transistor. At least one drain finger extends in a first direction on a first surface of the substrate and is configured to function as a collector for the bipolar junction transistor. At least one source finger extends in the first direction on the first surface of the substrate and is configured to function as an emitter for the bipolar junction transistor. The at least one source finger includes a pickup region that is configured to set a substrate potential.

Abstract: A system and method for a packaged device with harmonic control are presented. In one embodiment, a device includes a substrate and a transistor die coupled to the substrate. The transistor die includes a plurality of transistor cells. Each transistor cell in the plurality of transistor cells includes a control (e.g., gate) terminal. The device includes a second die coupled to the substrate. The second die includes a plurality of individual shunt capacitors coupled between the control terminals of the plurality of transistor cells and a ground reference node. The capacitance values of at least two of the shunt capacitors are significantly different.

Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.

Abstract: A mechanism is provided to determine orientation of a device that includes sources of electromagnetic interference. Data generated by one or more gyroscopes in the device, in conjunction with data generated by one or more accelerometers, can be used to generate an estimate of the change of orientation of the device from the time of a last accurate magnetometer reading. In one embodiment, in order to conserve system power, the gyroscope is kept powered down or in a stand-by state until receiving a control signal to power up. The control signal is provided in advance of the source of electromagnetic interference being powered up, thereby providing an accurate starting point from which magnetometer orientation estimates may be calculated during such interference.

Abstract: A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.

Abstract: An integrated circuit includes a first portion of a stacked ring oscillator coupled between a first supply voltage node and a common node, wherein the first supply voltage node provides a local supply voltage for the first portion and the common node provides a local ground for the first portion. The integrated circuit includes a second portion of the stacked ring oscillator coupled between the common node and a second supply voltage node wherein the common node provides a local supply voltage for the second portion and the second supply voltage node provides a local ground for the second portion. The integrated circuit also includes a voltage divider having a first resistive element coupled between the first supply node and the common node and a second resistive element coupled between the common node and the second supply node.

Abstract: A method and apparatus of audio processing is described. An audio processor may receive a multi-channel audio signal. In a first mode of operation, an audio processor may output a first audio signal on a first multi-channel audio output and a second audio signal on a second multi-channel audio output. In a second mode of operation, the audio processor may output a third audio signal on the first multi-channel audio output and a sub-woofer audio signal on at least one channel of the second multi-channel output.

Abstract: A microelectromechanical system (MEMS) gyroscope device includes a substrate having a surface parallel to a plane; first and second proof masses driven to slide back and forth past one another in a first directional axis of the plane, where the first and second proof masses respectively have a first and second recess in a respective side closest to the other proof mass; a pivot structure coupled to the first proof mass within the first recess and to the second proof mass within the second recess; an anchor between the first and second recesses and coupled to a mid-point of the pivot structure; and third and fourth proof masses driven to move toward and away from one another in a second directional axis of the plane that is perpendicular to the first directional axis; where the proof masses move in response to angular velocity in one or more directional axes.

Abstract: A method and apparatus are provided for controlling data flow by storing variable length encoded information bits in a circular buffer in a write operation to a virtual write address comprising a first wrap bit value appended by a current write address within the buffer address range and generating an interrupt alarm if the virtual write address crosses a virtual alarm address comprising a second wrap bit value appended by an alarm address within the buffer address range, where the first and second wrap bit values each toggle between first and second values every time the current write address or alarm address, respectively, wraps around the circular buffer, thereby synchronizing data flow in the circular buffer and/or preventing buffer overflow.