Abstract: Shielded and packaged electronic devices, electronic assemblies, and methods are disclosed herein. The shielded and packaged electronic devices include a packaged electronic device with a package surface and a plurality of electrically conductive package pads arranged on the package surface, a shielding dielectric layer extending in contact with the package surface and having a shielding layer surface and a plurality of openings that extends between the shielding layer surface and the plurality of electrically conductive package pads, and a plurality of electrical conductors that extends from the plurality of electrically conductive package pads and projects from the shielding layer surface. The electronic assemblies include a printed circuit board with a board surface and a plurality of electrically conductive board pads arranged on the board surface, the shielded and packaged electronic device, and an underfill dielectric layer. The methods include methods of manufacturing the electronic assemblies.

Abstract: A design verification system verifies an electronic device design based on a static model of the electronic device. The static model is an expression of the relationships between modules of the electronic device design and relationships between the behaviors of those modules that can be expressed as set of logical relationships. The static model does not rely on a time variable, but instead reflects a fixed set of relationships between the electronic device modules and between behaviors of the electronic device modules. The static model can be employed by a solver, that identifies whether or how the mathematical relationships of the static model can be reconciled, given a set of constraints. The solver results can be analyzed to identify whether there are errors in the device design, such as resource conflicts, failure of the design to achieve a desired configuration, and the like.

Abstract: A computing device comprises: a memory; a processor; an interpreter; and a Memory Management Unit. The interpreter is for controlling the processor to execute a program comprising at least one first instruction in a format that is not native to the processor and at least one second instruction in machine code that is native to the processor. The Memory Management Unit is adapted to control access by the processor to the memory and possibly also to peripherals when the at least one second instruction is executed.

Abstract: A technique that reduces the startup time of a processing system authenticates a proxy for an image stored in tracked memory instead of authenticating the image stored in the tracked memory. A controller generates an alteration log authentication code based on an alteration log that is updated prior to programming the image stored in tracked memory. The controller records an alteration log authentication code in secure memory. The alteration log is indirectly related to a most recent image stored in the tracked memory. Authentication of the image of the alteration log is used as a proxy for authentication of the image stored in tracked memory, which is performed only when the tracked memory is modified. Use of the contents of the alteration log as a proxy for the contents of tracked memory accelerates the startup time of the system.

Abstract: A lead frame for a packaged integrated circuit (IC) device has alternating first and second leads that protrude from a package body in respective first and second planes, where the second plane is parallel to and below the first plane. The first leads are formed into Gull Wing shaped leads and the second leads are formed into J-shaped leads. Inner lead portions of the first and second leads are maintained in the first plane with a tape. An inner lead portion of each of the second leads, proximate to and extending to the outer lead portion, is down-set, so that when the outer lead portion is pressed down by a mold tool to locate the outer lead portion of the second leads in the second plane, the inner lead portion of the second leads is maintained in the first plane and does not separate from the tape.

Abstract: A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a current conducting unit, coupled to the DC trigger circuit, that generates a first clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. The DC trigger circuit includes a surge detection circuit and a first amplification circuit. The surge detection circuit detects if a surge pulse occurs, and triggers the first amplification circuit to generate the trigger signal when the surge detection circuit detects a surge pulse.

Abstract: A sensor includes groups of sense elements coupled to one another to form multiple Wheatstone bridges, each being configured to produce an output voltage across first and second output nodes. A signal interface circuit for the sensor includes switched capacitor structures, one each of the switched capacitor structures being associated with one each of the Wheatstone bridges. Each switched capacitor structure includes a capacitor having first and second terminals, a first switch for selectively interconnecting the first node of an associated Wheatstone bridge with the first terminal of the capacitor, and a second switch for selectively interconnecting the second node of the associated Wheatstone bridge with the second terminal of the capacitor. A switch state element toggles the first and second switches between a charge state and a readout state to provide a readout voltage that is equivalent to a summation of the voltage outputs of the Wheatstone bridges.

Abstract: Embodiments of a switched-mode power supply and a method for operating a switched-mode power supply involve synchronizing a phase and frequency of an asynchronous controller of the switched-mode power supply with a clock signal of a synchronous controller of the switched-mode power supply while the asynchronous controller is in control of a power stage of the switched-mode power supply, concurrent with synchronizing the phase and frequency of the asynchronous controller with the clock signal of the synchronous controller, presetting a state variable of the synchronous controller while the asynchronous controller is in control of the power stage of the switched-mode power supply, and switching control of the power stage from the asynchronous controller to the synchronous controller after the phase and frequency of the asynchronous controller are synchronized with the clock signal of the synchronous controller and after the state variable of the synchronous controller is preset.

Abstract: There is disclosed a single-wire Interface bus transceiver system comprising: an I2C master, a master transceiver, a signal wire, a slave transceiver and an I2C slave, wherein the master transceiver is adapted to encode master data SDA and master clock SCL received from I2C master using Manchester code, generate master single wire signal and transfer it to the slave transceiver through the signal wire, the master transceiver is also adapted to decode Manchester-encoded slave signal received from the signal wire and transfer the decoded slave data to I2C master; the slave transceiver is adapted to encode slave data received from I2C slave using Manchester code, generate slave single wire signal and transfer it to the master transceiver through the signal wire, the slave transceiver is also adapted to decode Manchester-encoded master signal received from the signal wire, generate the recovered master clock and transfer the decoded master data and recovered master clock to I2C slave.

Abstract: A touch sensitive capacitive keypad system (300) is provided with a keypad sensing electrode (304) disposed within sensing proximity of multiple electrodes (E0-E9) and formed under a keypad touch panel having defined key areas, where the electrodes are respectively aligned with the defined key areas to facilitate touch detection at the keypad touch panel with a controller (310) that is configured to determine which of the plurality of defined key areas is being touched by detecting a predetermined signal characteristic at the keypad sensing electrode (304) before sequential scanning the plurality of capacitive key electrodes to identify which capacitive key electrode is aligned with a defined key area being touched.

Abstract: According to a first aspect of the present disclosure, a apparatus is provided, the apparatus comprising a reader and a controller operatively coupled to the reader, wherein the reader is configured to receive certificate data from an external tag and to provide said certificate data to the controller, and wherein the controller is configured to receive said certificate data from the reader, to verify whether the certificate data are valid, and to enable operation of the apparatus if the certificate data are valid. According to a second aspect of the present disclosure, a corresponding method for controlling the operation of an apparatus is conceived. According to a third aspect of the present disclosure, a corresponding computer program product is provided.

Abstract: A display control apparatus comprising at least one memory element within which image data is stored, at least one display controller arranged to read from the, or each, memory element the image data and to output display data generated from the read image data to at least one display device. The display control apparatus further comprises at least one interface component via which the display controller is arranged to read image data from the memory element. The display control apparatus further comprises at least one interface bandwidth control component arranged to measure image data flow over the interface component from the memory element to the display controller, and configure a bandwidth for image data flow over the interface component from the memory element to the display controller based at least partly on the measured image data flow.

Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.

Abstract: A control arrangement is disclosed for a switch mode power supply (SMPS) operable in a burst mode and comprising an opto-coupler configured to transfer, from a secondary side to a primary side of the switch mode power supply by means of an LED current, a control signal indicative of a time-varying error between a reference signal and a signal indicative of an actual value of an output parameter, the control arrangement comprising: an error amplifier configured to operate as a proportional-integrating error amplifier to determine the LED current from the time-varying; and a feedback loop configured to adjust the magnitude of the LED current between bursts by modifying the time-dependant error. A SMPS comprising such a control arrangement, and a corresponding method is also disclosed.

Abstract: A semiconductor device includes a lead frame having leads arranged in an array that has columns extending in a first direction and rows extending in a second direction. Each lead includes a bond pad portion and a solder pad portion down-set from the bond pad portion. The solder pad portion horizontally extends from the bond pad portion in the first direction. A semiconductor die is mounted on a set of the plurality of leads and electrically connected to the bond pad portion of at least one of the plurality of leads. The semiconductor die, and the plurality of leads are encapsulated by a molding material, wherein the molding material defines a package body, and the solder pad portion of each lead is exposed at a back side of the package body.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.

Abstract: A flip chip circuit comprising: a semiconductor substrate; a power amplifier provided on the semiconductor substrate; and a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry. At least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate.

Abstract: A semiconductor device comprising a switch and a method of making the same. The device, has a layout having one or more rectangular unit cells. Each unit cell includes a gate having a substantially cross-shaped part comprising four arms that divide the unit cell into quadrants; and a substantially loop-shaped part, wherein a center of the cross-shaped part is located inside the loop-shaped part, and wherein the loop-shaped part intersects each arm of the cross-shaped part to divide each quadrant into an inner region located inside the loop-shaped part; and an outer region located outside the loop-shaped part. Each unit cell also includes a substantially loop-shaped active region forming a source and drain of the switch. Each unit cell further includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the source and drain.

Abstract: A power converter having a switch network, a resonant tank network, and a controller performs in situ determination of the Q-factor of the resonant tank network. The controller excites transitory damped oscillations of the resonant tank network by applying a limited number of ON-pulses to the transistor switches of the switch network. The controller then samples the envelope of the waveform corresponding to the excited transitory damped oscillations and processes the resulting set of digital signal samples to determine the Q-factor of the resonant tank network. The Q-factor determination can be repeated to prevent the power converter from being operated under undesirable operating conditions caused by certain ambient factors, such as the unexpected presence of metal objects in the immediate vicinity of the power converter.

Abstract: A processing system includes a general purpose instruction based data processor, an input configured to receive a command written by the data processor, a timer manager controller configured to receive the command and to execute the command, and a debug interrupt timer controller (DITC) configured to determine that the command is directed to the DITC and to store configuration information that associates the command with an element of the processing system that is a source of the command, where the configuration information is included in the command.