Abstract: A method of undervoltage detection includes detecting a voltage level for a power supply of a system, placing the system in an undervoltage state if the voltage level is below an undervoltage threshold, activating a load of the system at a first power level if the detected voltage level exceeds a first activation threshold and if the system resides in the undervoltage state, and activating the load at a second power level if the detected voltage level exceeds a second activation threshold.

Abstract: A system to enable an integrated development environment to efficiently parse error expressions generated by tools used to generate processing environment-specific executable code, where the tools are external to the integrated development environment, is provided. The system groups error parsers configured to parse the error expressions into two groups: error parsers that handle output from a tool using a single output line of regular expression, and error parsers that require something more than a single output line of regular expression to determine the nature of an error. Embodiments of the system can determine whether a particular output regular expression should be analyzed by a selected set of the error parsers by comparing the output regular expression against a concatenated list of all the regular expressions corresponding to those error parsers that handle output from the tool using a single output line of regular expression.

Abstract: A design verification system simulates operation of an electronic device to identify one or more power characteristic vs. temperature (PC-T) curves for the electronic device. Each of the one or more PC-T curves indicates, for a particular reliability characteristic limit, a range of power characteristic values over a corresponding range of temperatures that are not expected to result in the reliability characteristic limit being exceeded. Based on the one or more PC-T curves, the design verification system sets a range of power characteristic limits, over a corresponding range of temperatures, for the electronic device. During operation, the electronic device employs a temperature sensor to measure an ambient or device temperature, and sets its power characteristic (voltage or current) according to the measured temperature and the power characteristic limits.

Abstract: A non-volatile memory (NVM) system has a main NVM sector with multiple memory segments, a redundant NVM sector for storing recovery records, an address-matching circuit having multiple memory sections, each adapted to store a pair of main and substitute addresses, and an NVM controller. The NVM controller is configured to determine if a first memory segment of the main NVM sector is no longer usable and, consequently (i) create a recovery record for storage in the redundant NVM sector that includes the address of the first memory segment and the data associated with the first memory segment, and (ii) add a pair of main and substitute addresses to the address-matching circuit, where the main address is the address of the first memory segment and the substitute address identifies a substitute location for the data associated with the first memory segment.

Abstract: An asynchronous data transfer system includes a bus interface unit (BIU), a FIFO write logic module, a write pointer synchronizer, a write pointer validator, a FIFO read logic module, and an asynchronous FIFO buffer. The FIFO buffer receives a variable size data from the BIU and stores the variable size data at a write address. The FIFO write logic module generates a write pointer by encoding the write address using a Johnson code. The FIFO read logic module receives a synchronized write pointer at the asynchronous clock domain and generates a read address signal when the synchronized write pointer is a valid Johnson code format. The FIFO buffer transfers the variable size data to a processor based on the read address signal.

Abstract: Aspects of the present disclosure are directed to circuits, apparatuses and methods for generating communication signals resistant to early-detect-late-commit attacks. An example embodiment, a plurality of data symbols is generated that includes first and second data symbols. A communication signal is generated that is decodable according to a mapping of the first and second data symbols to respective first and second waveforms. The first waveform has a leading edge that is indicative of the first waveform, and second waveform has a second leading edge that is indicative of the second waveform. In generating the communication signal, a first portion of the communication signal is modulated according to the first waveform for the first data symbol. A second portion of the communication signal is modulated, for the second data symbol, according to a modified second waveform having a leading edge that is indicative of the first waveform.

Abstract: A power factor controller is disclosed, in which error feedback is provided my means of a parallel combination of at least two error feedback channels. By providing at least two error feedback channels, the stability associated with, for instance, a continuously integrated feedback loop with relatively long time constant, may be combined with a fast transient response associated with, for instance, a sample-and-hold error feedback. A method of operating such a power factor controller is also disclosed.

Abstract: A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz.

Abstract: Transistor-based semiconductor devices, such as systems on chips, may be supplemented with a reset request mechanism to prevent a reset from causing the semiconductor device to enter into an uncertain, or fail, state. More particularly, a method or mechanism may modify a requested reset for a semiconductor device based on a state of the semiconductor device to prevent the semiconductor device from entering an uncertain, an undesired, or a failed state when the reset is effected with regard to the semiconductor device.

Abstract: The invention provides a method for launch-off-shift at-speed scan testing for at least two scan chains of an integrated circuit comprises iteratively shifting set values for functional elements of a first one of the scan chains clocked with a shift clock, iteratively shifting set values for functional elements of a second one of the scan chains clocked with the shift clock, launching an at-speed scan test clocked with a functional clock for the first one of the scan chains at a last shift cycle of the first one of the scan chains, delaying the last shift cycle for the second one of the scan chains for a predetermined time span, launching an at-speed scan test clocked with a functional clock for the second one of the scan chains at the last shift cycle of the second one of the scan chains, capturing the sample values of the functional elements of the first and second scan chains after the last shift cycle of the scan chains.

Abstract: A sigma-delta modulator comprising a plurality of filter stages in series with each other, wherein at least one of the plurality of filter stages is configured to provide a filter-output-signal; and a plurality of gain stages, each gain stage configured to provide a gain-output-signal. The sigma-delta modulator also includes a filter-output-switching-element configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages; and a plurality of filter-input-switching-elements. Each of the plurality of filter-input-switching-elements is associated with one of the plurality of filter stages, wherein the plurality of filter-input-switching-elements are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages.

Abstract: A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry.

Abstract: An ESD protection device comprising an SCR-type circuit including a PNP transistor and NPN transistor incorporates a Zener diode which permits the circuit to operate at comparatively low trigger voltage thresholds. Zener diode breakdown voltage is controlled by doping levels in a doped area of an N-type well. One or more diodes connected in series between the SCR circuit and the input/output terminal of the device advantageously raises the snapback voltage of the SCR circuit. The use of nitride spacers between doped regions instead of gate oxide technology significantly reduces unwanted leakage currents.

Abstract: A system for concurrently testing multiple semiconductor components includes multiple testers, each including a processor and a memory configured to store and execute control signals for completing testing of one of the semiconductor components, a tester side docking board, and a tester communication port. A handler has multiple test sites, each of which is configured to receive one of the semiconductor components, a handler side docking board, and a handler communication port. A controller is located externally from the testers and the handler and is in communication with each of the testers and the handler through the tester and handler communication ports. Communication between each of the testers and the handler occurs through the controller, and each of the testers is connected, via the tester side docking board, to a corresponding one of the semiconductor components through the handler side docking board.

Abstract: A method of operating a data processing system comprises: processing data words and switching between contexts; assigning a context signature Sig to any pair formed of a data word and a context; reading, within a current context, a data record from a memory unit, the data record comprising a payload data word and a protection signature; providing, as a verification signature, the context signature Sig of the payload data word and the current context; checking the verification signature against the protection signature; and generating an error signal if the verification signature differs from the protection signature.

Abstract: A semiconductor device composed of a through-substrate-via (TSV) interconnect, and methods for forming the interconnect.

Abstract: A voltage regulation system includes a voltage regulator configured to output a control signal indicating whether a voltage based on output of the voltage regulator is lower than a specified value. A charge pump is configured to output a voltage and a charging current. A pump monitor is configured to receive the control signal and the output voltage of the charge pump, and activate the charge pump when the control signal indicates the voltage based on output of the voltage regulator is lower than a specified value and the output voltage of the charge pump is lower than a threshold value.

Abstract: A receiver and method for a wireless signal transmission system use digital amplitude modulation of a base band signal having a symbol clock frequency. The receiver includes a reference generator which generates a local reference frequency, a mixer to extract the base band signal, a high pass filter to suppress a DC component, an amplifier, an analog-to-digital converter and a digital signal processor to receive digital signals and extract symbols. A base band signal rotation detection circuit detects rotation of the base band signal upstream of the high pass filter. The digital signal processor determines a symbol clock phase by generating a coarse estimate of the symbol clock phase and correcting the coarse estimate based on detected rotations of the base band signal. A determination that the symbol clock phase corresponds to a complete rotation is used in relation to the extraction of symbols.

Abstract: A method for a near field communication circuit includes entering a low power mode and subsequently determining to exit the low power mode. The method further includes generating an open loop clock signal and providing the open loop clock signal to circuits of the near field communication circuit during a low power mode exit duration. Subsequently a reference clock signal is received from a host and used to clock the near field communication circuit.

Abstract: An electrostatic discharge protection device including a silicon controlled rectifier. In one example, the silicon controlled rectifier includes a first n-type region located in a semiconductor substrate. The silicon controlled rectifier also includes a first p-type region located adjacent the first n-type region in the semiconductor substrate. The silicon controlled rectifier further includes an n-type contact region and a p-type contact region located in the first n-type region. The silicon controlled rectifier also includes an n-type contact region and a p-type contact region located in the first p-type region. The silicon controlled rectifier further includes a blocking region having a higher resistivity than the first p-type region. The blocking region is located between the n-type contact region and the p-type contact region in the first p-type region for reducing a trigger voltage of the silicon controlled rectifier.