Abstract: A device in which an electronic circuit positioned within a cavity of a package housing is encased by a bubble restrictor material, with a media resistant material overlaying the bubble restrictor material. The bubble restrictor material functions to inhibit the formation and growth of moisture-related bubbles within the material, including at the interfaces of the material and surfaces within the package housing. The media resistant material is resistant to physical and chemical alterations by media within an external environment to which the device is exposed. The media resistant material and bubble resistant material function to transfer a sensed characteristic of the media to the electronic circuit.

Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

Abstract: The invention provides a reception method and apparatus which provides a series of frequency shifts and filtering operations to sideband signals (lower, upper, and middle), to enable detection if the central part of a signal is analog or digital, and to enable effective co-channel interference compensation. The invention enables (H)IBOC signals for example to be processed with a narrower bandwidth and therefore a lower processing clock speed and complexity is made possible compared to the conventional (H)IBOC-signal processing approach.

Abstract: A continuous-time linear equalizer implementing enhanced analog delay cells with gain-peaking characteristics and a constant delay time. A receiver feed-forward equalizer architecture implements a gain-stage chain, analog multipliers for correcting coefficients, and a linear combiner as an analog summation circuit. Each of the gain stages produces linear gain peaking and presents a constant delay-time (through calibrations) at each stage. Each delay cell includes a transconductance stage configured to convert a differential input voltage signal to a differential output current signal, wherein the transconductance stage includes a differential pair of first and second transistors coupled in a source degeneration configuration, a negative resistance network coupled in parallel with a tunable resistor network, and shunt inductive circuitry coupled in parallel with the negative resistance network.

Abstract: A circuit for delivering power to a load from a wireless power supply comprises an inductor coil for placing in the electromagnetic field of an inductor coil of a supply and a switchable capacitor bank with capacitors switchable at least between a series and a parallel configuration. The voltage across the capacitor bank is used as a feedback control parameter for controlling the capacitor bank switching. A voltage regulator is used to supply the load with a constant voltage power supply derived from the capacitor bank output.

Abstract: An integrated circuit includes a scan chain, a clock divider circuit, and clock selection circuitry. The scan chain includes a plurality of dual edge flip flops, wherein each dual edge flip flop includes a data input, a scan input, a clock input, and data output. The clock divider circuit is coupled to receive a test clock and is configured to divide the test clock to provide a divided test clock. The clock selection circuitry has a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided test clock and the system clock as a clock signal to the clock inputs of the scan chain based on the scan enable signal.

Abstract: A segmented driver including at least one drive pin and a sense pin, a driver circuit, a comparator, and a controller. The driver circuit activates a selected drive level between the drive pins and a reference node. The comparator compares a voltage of the sense pin with a threshold voltage and provides a threshold indication when the voltage of the sense pin reaches the threshold voltage. The controller commands the driver circuit to activate a first drive level in response to an off indication, and commands the driver circuit to switch to a second, lower drive level in response to the threshold indication. The driver circuit may be implemented using low resistive current devices. Multiple drive pins may be included, each for selectively activating a corresponding drive path to adjust drive level. The threshold voltage may be set using a current source and resistor, and may be adjusted for temperature.

Abstract: An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.

Abstract: A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).

Abstract: An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.

Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.

Abstract: A clock modulation module and method for generating a modulated clock signal are provided. The clock modulation module comprises a comparator arranged to receive at a first input thereof a waveform signal, the waveform signal comprising a frequency representative of a frequency of a reference timing signal. The comparator is further arranged to receive at a second input thereof a reference voltage signal, and to output a modulated timing signal based on a comparison of the waveform signal and the reference voltage signal. Wherein the clock modulation module is arranged to output a modulated clock signal derived at least partly from the modulated timing signal output by the comparator.

Abstract: A device and method for performing a keyed cryptographic operation mapping an input message to an output message including a first and a second round, wherein the cryptographic operation includes a key scheduling method that produces round keys based upon the encryption key, including: instructions for receiving a first input by the first round; instructions for receiving a second input by the first round; instructions for outputting the second input as a third input to the second round; instructions for performing a first cryptographic operation on the second input using a first static round key to produce a first cryptographic output; and instructions for combining first input, the first cryptographic output, and a second encoded dynamic round key to produce a fourth input to the second round, wherein the second encoded dynamic round key is produced by inputting an encoded dynamic encryption key into the key scheduling method.

Abstract: A buffer or voltage protection circuit, a circuit including same, and an associated method of operation are disclosed. In one example embodiment, the integrated circuit includes a first input terminal, a first circuit portion having a second input terminal, and a second circuit portion. The second circuit portion includes a transistor device having first, second, and third ports, where the first and second ports are respectively electrically coupled to the first input terminal and second input terminal, respectively. Additionally, the second circuit portion also includes a diode-type device that is electrically coupled between the third port and either a power source or a power input terminal, and a buffer/driver circuit and a capacitor coupled in series between the third and second ports. The second circuit portion operates to prevent the second input terminal from being exposed to an undesirably-high voltage level.

Abstract: Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.

Abstract: Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate.

Abstract: A memory system has a first plurality of non-volatile random access memory (NVRAM) cells. Each NVRAM cell has a volatile portion coupled to a corresponding non-volatile portion. A non-volatile indicator circuit provides information as to whether the first plurality of NVRAM cells has the most recent data written into NVRAM cells in the non-volatile portions.

Abstract: In a system on chip SoC, a memory control unit connected between the memory unit and the processing unit controls access to the memory unit. An update request received or generated by the processing unit triggers an update operation which comprises appending an update enabling record to a sequence of update records in the log region, writing new program code to the memory unit, and appending an update completion record to a sequence of update records. Write access to the log region is disabled if a fault is detected in the SoC during the update operation.

Abstract: In an object finding method for finding an object (20) provided with a contactless readable data carrier (2), descriptive data (INF) stored in the data carrier (2) are transmitted to a reading device (1) when the data carrier (2) comes into the effective area of the reading device (1). In the reading device (1) the descriptive data (INF) received from the data carrier (2) are compared with predefined profile data (PRO) in respect of the fulfillment of at least one comparison condition. Upon fulfillment of the comparison condition the reading device (1) subsequently issues a notification (TRIG).

Abstract: An approach is provided in which a hybrid mixed signal equivalence checking system partitions a mixed signal reference model and a mixed signal model under verification into analog sections and digital sections. The hybrid mixed signal equivalence checking system simulates the analog sections from the two different models to determine analog equivalence. As such, the hybrid mixed signal equivalence checking system verifies digital equivalence between the digital reference section and the digital section model under verification in response to evaluating one or more difference functions that represent at least a portion of the first digital section and the second digital section. As a result, the hybrid mixed signal equivalence checking system verifies equivalence between the mixed signal reference model and the mixed signal model under verification based upon the verified analog equivalence and the verified digital equivalence.