Abstract: In an object finding method for finding an object (20) provided with a contactless readable data carrier (2), descriptive data (INF) stored in the data carrier (2) are transmitted to a reading device (1) when the data carrier (2) comes into the effective area of the reading device (1). In the reading device (1) the descriptive data (INF) received from the data carrier (2) are compared with predefined profile data (PRO) in respect of the fulfillment of at least one comparison condition. Upon fulfillment of the comparison condition the reading device (1) subsequently issues a notification (TRIG).

Abstract: Integrated circuit (IC) modules and methods for manufacturing the IC modules are described. In an embodiment, an IC module includes a substrate with contact gaps on which an IC die is attached with electrical connections between the IC die and the substrate. The IC module further include an encapsulation that encloses the IC die and fills first portions of the contact gaps, where the first portions of the contact gaps are located within an area of the substrate defined by the encapsulation. Second portions of the contact gaps, which are located outside of the area of substrate defined by the encapsulation, are filled with a filling material.

Abstract: A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data.

Abstract: Embodiments of three dimensional (3D) System-in-Package (SiPs) and methods for producing 3D SiPs having improved heat dissipation capabilities are provided. In one embodiment, the 3D SiP includes a heat-dissipating structure having a first principal surface and a second principal surface opposite the first principal surface. The backside of a first microelectronic device is disposed adjacent and thermally coupled to the first principal surface of the heat-dissipating structure, while the backside of a second microelectronic device is disposed adjacent and thermally coupled to the second principal surface of the heat-dissipating structure. During operation of the 3D SiP, heat generated by the microelectronic devices is conductively transferred to and dissipated through the heat-dissipating structure.

Abstract: A circuit including and a method utilizing an improved bootstrap topology provide power to a high side (HS) driver for high efficiency applications. The improved bootstrap topology includes a transfer capacitor to store charge and to recharge a bootstrap capacitor, which provides power to the HS driver. The improved bootstrap topology also includes a resistor connected to the transfer capacitor to charge the transfer capacitor from a voltage source and to isolate the transfer capacitor from high voltage pulses.

Abstract: Stacked microelectronic package assemblies are provided, as are methods for producing stacked microelectronic package assemblies. In one embodiment, the stacked microelectronic package assembly includes a base package layer onto which a stacked bridge device is stacked. The base package layer includes, in turn, a first microelectronic package and a second microelectronic package positioned laterally adjacent the first microelectronic package. The stacked bridge device extends over the first and second microelectronic packages. A first terminal of the stacked bridge device is soldered to or otherwise electrically joined to a first backside contact of the first microelectronic package, and a second terminal of the stacked bridge device is soldered to or otherwise electrically joined to a second backside contact of the second microelectronic package.

Abstract: It is provided an apparatus for transferring energy to an accumulator, the apparatus having a core and a wire wound around the core thereby forming a coil, wherein the coil is adapted to receive energy from a magnetic field, wherein the wire is connectable to the accumulator to transfer the received energy to the accumulator. A charging station for generating a magnetic field for transferring energy to an accumulator is provided, and a system for charging an electric accumulator is provided, wherein the system includes an apparatus as described above; and a charging station having a further wire wound such as to form a further coil.

Abstract: A method of regulating an output voltage of an alternator. The method comprises measuring first and second external contacts of the alternator regulator module operably coupled to first and second output contacts of the alternator respectively during an ON state of an excitation cycle for the alternator, measuring a second voltage across the first and second external contacts of the alternator regulator module during an OFF state of an excitation cycle for the alternator, deriving an average voltage value of the first and second voltage measurements, and deriving an offset value based at least partly on the derived average voltage value. The method further comprises measuring an instantaneous voltage across the first and second external contacts of the alternator regulator module, and configuring a control signal for regulating the output voltage of the alternator based at least partly on the instantaneous voltage measurement and the derived offset value.

Abstract: An embodiment of a packaged RF amplifier device includes a device substrate, a transistor die coupled to the device substrate, and an isolation structure coupled to the transistor die. The transistor die has a top die surface, a bottom die surface, a semiconductor substrate, first and second transistors formed in the semiconductor substrate, a conductive structure at the top die surface and positioned between the first and second transistors, and a low resistance path that extends vertically through the semiconductor substrate between the conductive structure and the bottom die surface. The isolation structure is coupled to the conductive structure and extends into an area above the top die surface between the first and second transistors. The isolation structure may be a wirebond fence, a conductive wall, conductive pillars or vias, or a plated trench that extends vertically upward from the conductive structure. The device may be encapsulated with molding compound.

Abstract: A power regulator includes an output terminal to provide a regulated voltage, a first control unit to control a first operation mode, a second control unit to control a second operation mode, and a detection unit connected to the output terminal. The detection unit detects, at start-up, whether or not an external inductor is connected to the output terminal, activates the first operation mode when an external inductor is detected, and activates the second operation mode when no external inductor is detected. The detection unit also detects in which of at least two distinct inductance ranges the inductance of the detected inductor lies so as to provide inductance dependent control in the first operation mode.

Abstract: A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.

Abstract: A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first metal and oxygen to form the metal oxide having grains and further adding a catalyst during the combining. The catalyst causes the grains to be bigger than would occur in the absence of the catalyst. A conductive layer (202) is formed over the metal oxide.

Abstract: A storage element with monitoring circuit, comprising a previous state information storage element configured to record a previous state of a monitored state information storage element, a state change indication unit having a clock input terminal coupled to the clock signal input interface, a state change indication unit being configured to generate a state change indication signal indicative of whether the monitored state information storage element shall have performed a state change by observing the data at a data input interface and a data output terminal, and a state change confirmation unit configured to generate a storage fault indicator by observing the data output terminal of the monitored state information storage element and the data output of the previous state information storage element and checking whether the result of this observation is in line with the state change indicator.

Abstract: An antenna structure is disclosed. In the embodiment, the antenna structure includes a substrate and an antenna that is formed on the substrate, the antenna having a first end and a second end that are separated. The antenna structure also includes a heating element formed on the substrate with at least a portion of the heating element being located in the separation between the first and second ends of the antenna, with the heating element being electrically separate from the antenna.

Abstract: A glitch filter circuit has a filter/delay part that always operates on rising or falling pulses for both rising edges and falling edges of the input signal. In this way, the filter delay can be made symmetrical and the circuit will have no duty cycle distortion. The rise and fall delays will track each other when there are PVT (Process, Voltage and Temperature) variations.

Abstract: A flip-flop (10) is disclosed comprising a slave latch (30) and a master latch (20). Each of the slave and master latch comprise a pair of cross-coupled logic gates (21, 22, 31, 32). A cross coupling connection of the slave or master latch (30, 20) comprises a resistive element (8, 9, 11, 12) arranged to reduce the sensitivity of the flip-flop (10) to a current injection.

Abstract: An apparatus is disclosed that includes a clock distribution circuit configured to shift a first clock signal in the first voltage domain to a second voltage domain to produce the second clock signal. The second voltage domain extends outside of the first voltage domain. A set of flip-flops operating in the first voltage domain, each including a master latch, a slave latch, and a clock node is coupled to receive the second clock signal. Each flip-flop includes a master pass transistor configured to pass a value from an input of the flip-flop to an input of the master latch when the second clock node is set to a first value. Each flip-flop also includes a master pass transistor configured to pass the value from an output of the master latch to an input of the slave latch when the second clock node is set to a second value.

Abstract: A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type.

Abstract: A saturation edge detection circuit for testing a saturation level in an insulated gate bipolar transistor (“IGBT”) includes a first input operable to receive an on signal, a second input coupled to an IGBT driver circuit, and an output coupled to a control electrode of the IGBT. The output indicates a change in a state of a saturation voltage associated with the IGBT during operation of the IGBT.

Abstract: A method and apparatus are provided for manufacturing a packaged electronic device (200) which includes a carrier substrate (120) in which conductive interconnect paths (122) extend between first and second opposed surfaces, an integrated circuit die (125) affixed to the first surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, and an array of conductors (110), such as BGA, LGA, PGA, C4 bump or flip chip conductors, affixed to the second surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, where the array comprising a signal feed ball (112) and an array of shielding ground balls (111) surrounding the signal feed ball.