Abstract: A charge pump comprises one or more pump stages for providing a negative boosted output voltage. Each of the one or more pump stages comprises a P-channel transistor formed in an isolated P-well and an N-channel transistor coupled in series with the P-channel transistor. Forming the P-channel transistor in the isolated P-well essentially eliminates a raised threshold voltage due to body effect.

Abstract: A method provides access to an integrated circuit which may comprise a storage containing an unalterable first security key and a memory containing a second security key. The method may comprise: checking the second security key by comparing the first security key and the second security key, if the second security key is valid, providing access to the integrated circuit, optionally depending on the validity of an access key, and if the second security key is invalid, enabling erasing the memory, and storing in the memory a new second security key which corresponds to the first security key. Erasing the memory may be followed by checking the erasing for completeness.

Abstract: Mobile devices such as mobile phones have always-on modes using sensors which respond to changes in the environment. A mobile device is described comprising a loudspeaker; a controller having an input coupled to the loudspeaker. The controller is operable in a first mode of operation to detect an electrical signal generated by the loudspeaker in response to an acoustic input signal. This signal can be used to activate further circuitry. Using a loudspeaker as an acoustic sensor may reduce the power consumption of the mobile device.

Abstract: A controller for a switched mode power converter is disclosed, the switched mode power converter comprising a transformer defining a primary side circuit and a secondary side circuit, the primary side circuit comprising a primary switch, the secondary side circuit comprising a synchronous rectification switch, the controller comprising: a baseline off-set circuit configured to provide a baseline timing off-set between opening the synchronous rectification switch and closing the primary switch; a peak current detector configured to detect a peak negative current in the secondary side circuit; and a feedback circuit configured to add an off-set adaptation to the baseline timing off-set to provide an adapted timing off-set, wherein the feedback circuit is configured to adjust the off-set adaptation to minimize the negative peak current. A switched mode power converter and electronic equipment using such a controller is also disclose, as is a method for controlling a switch mode power converter.

Abstract: A current generator circuit includes at least one current generation component arranged to generate an output current of the current generator circuit, at least one absolute current calibration component arranged to enable calibration of an absolute current value of the output current, and at least one temperature coefficient calibration component arranged to enable calibration of a temperature coefficient characteristic of the output current. The at least one temperature coefficient calibration component is further arranged to be in a passive state at a reference temperature.

Abstract: A device has a protection unit for controlling access to a memory. Indirect memory access requests have control data indicative of a memory access control register to be written to provide indirect access to a target memory and requested address data indicative of at least one memory address of the target memory to be accessed. The protection unit contains protection data defining access rights of source units to access specified address ranges of the target memory, and a system bus interface interfacing to a source unit and a memory bus interface interfacing to the target memory via a controller. The protection unit has a control monitor for detecting an indirect memory access request, and an indirect address monitor for comparing requested address data to specified address ranges and subsequently grant the indirect memory access in accordance with access rights of the respective source unit.

Abstract: An EtherCAT packet forwarding system with distributed clocking is provided. The system comprises a master device and a plurality of slaves. The master comprises a processing port and a forward port for being respectively coupled to the at least two Ethernet ports of the master device in a redundant ring topology. The slaves comprise an internal clock indicating a current time, and a slave memory comprising a processing timestamp variable, a forwarding timestamp variable, a temporary timestamp variable and a copy-direct bit.

Abstract: An apparatus includes a swing control circuit, a slew control circuit, and a driver circuit. The swing control circuit is configured and arranged to be powered by an input supply voltage, to receive an input data signal and, in response, to generate a first internal signal having a swing level corresponding to the input supply voltage. The slew control circuit, including a switched capacitor circuit, is configured and arranged to receive the first internal signal and, in response, to generate a second internal signal using the switched capacitor circuit that is configured to set a slew rate for the second internal signal. Further, the driver circuit is configured and arranged to receive the second internal signal and, in response, to generate an output signal that is based upon the swing level and the slew rate of the second internal signal.

Abstract: Switching circuits are implemented in a manner that facilitates fast switching, which can be effected while also maintaining relatively low power dissipation. As may be implemented in connection with one or more embodiments, an apparatus includes a transistor connected between an input port and an output port, and a gate that switches between on and off states. A charge storage circuit stores a charge, and a switching circuit operates by switching the transistor between the on and off states as follows. In a first charging mode, a voltage is coupled across the charge storage circuit and a charge is stored therein, while decoupling the transistor from the charge storage circuit. In a second discharge mode, the transistor is switched from the off state to the on state, while coupling the stored charge across the gate and one of the source and drain of the transistor.

Abstract: Devices, methods and systems are provided for processing measurement data. An exemplary device includes a first module to provide data and an interrupt, a control module coupled to the first module to obtain the data from the first module and provide an indication after obtaining the data, and an interrupt control module coupled to the first module and the control module to notify the first module to clear the interrupt in response to the indication from the control module.

Abstract: A method of testing software uses a debugger and a breakpoint handler. The debugger inserts a breakpoint in a target application and enters at least one filtering condition associated with the breakpoint in a data structure. When during execution the target application encounters a breakpoint at an address, the target application transfers execution to the breakpoint handler. The breakpoint handler uses the address to retrieve filtering conditions from the data structure, executes code for evaluating the filtering condition, and transfers execution back to the target application if the filtering condition is not met.

Abstract: Aspects of the disclosure are directed to detecting interactions with signals, such as by an attacker attempting to gain access to a vehicle. Signal waveforms used for authentication are evaluated, for communications between respective circuits. Possible interaction by a third circuit is analyzed by detecting variations in characteristics of a leading portion of a data symbol relative to known characteristics of the leading portion of the data signal. A condition indicative of whether the signal waveform has been interacted with and retransmitted is determined, based on the detected variations. For instance, if the variations are indicative of a known type of variation induced by interaction and retransmission, such interaction and transmission can be detected. Where the determined condition is not deemed an attack, an output signal that provides vehicle access is generated based on the determined condition.

Abstract: A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a body region disposed in the semiconductor substrate and to which a voltage is applied during operation and in which a channel is formed during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the body region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the body region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the body region.

Abstract: There is described a driver for a switched capacitor circuit (230, 330), the driver comprising (a) a voltage amplifier (210, 310) comprising a signal input (212, 312), a feedback input (214, 314) and an amplifier output (216, 316), and (b) a feedback network (220) coupled between the amplifier output (216, 316) and the feedback input (214, 314). The feedback network comprises a track-and-hold circuit (222) adapted to mask a voltage dip occurring at the amplifier output (216, 316) at the beginning of a switched capacitor circuit charging phase. There is also described a switched capacitor circuit comprising such a driver, a sensor device, and a method of driving a switched capacitor circuit.

Abstract: High frequency detection of interrupts includes incrementing a count by a first number in response to at least one interrupt. The count is decremented by a second number in response to a clock if the count is greater than zero. An interrupt rate is determined from the count. A fault collection unit (FCU) is updated when the interrupt rate exceeds a threshold.

Abstract: Example apparatus for power-domain assignment, having: a first bus-to-switch interface; a second bus-to-switch interface; a first power-domain bus, coupled to the first bus-to-switch interface; a second power-domain bus, coupled to the second bus-to-switch interface. A set of I/O signal level shifters, coupled between the first and second power-domain buses; a switch including, a set of IP block power coupling outputs; a set of IP block I/O signal paths; and a selection signal input. The switch is coupled to the first and second bus-to-switch interfaces. Wherein, in response to receiving a first signal on the selection signal input, the switch is configure to couple the first power-domain bus to the set of IP block power coupling outputs; and wherein, in response to receiving a second signal on the selection signal input, the switch is configure to couple the second power-domain bus to the set of IP block power coupling outputs.

Abstract: Apparatuses, methods, and systems are configured to perform unambiguous parameter sampling in a heterogeneous multi-core or multi-threaded environment by masking one or more thread requests; and, in response to bus activity ceasing for the one or more masked thread requests and completing any routine being processed for the one or more masked threads, processing a command by executing at least one of a command routine or a command thread, wherein the command routine or the command thread reads the parameter using thread atomicity with deterministic synchronization. One or more thread requests may be selected for masking by monitoring thread activity for each of a plurality of threads.

Abstract: A phase locked loop is disclosed comprising: a phase detector, loop filter and a frequency controlled oscillator. The phase detector is configured to determine a phase difference between a reference signal and a feedback signal. The loop filter is configured to perform a filtering operation on a signal derived from the phase difference and to provide a control signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The phase locked loop further comprises a lock detector, including: a phase lock detector configured to receive a first signal from the phase locked loop, and to derive a phase lock signal from the first signal; a frequency lock detector configured to receive a second signal from the phase locked loop, and to derive a frequency lock signal from the second signal.

Abstract: A semiconductor device includes a substrate having a first dopant type, a first gate electrode and second gate electrode formed over the substrate and spatially separated from each other, a first region of a second dopant type, having a pocket of the first dopant type, formed in the substrate between the first and second gate electrodes, the pocket being spaced apart from the first and second gate electrodes, a silicide block over the first region, a source region formed in the substrate on an opposing side of the first gate electrode from the first region and having the second dopant type, a drain region formed in the substrate on an opposing side of the second gate electrode from the first region, the drain region having the second dopant type, and a second pocket of the first dopant type formed in the drain region adjacent to the second gate electrode.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.