Abstract: A method of forming an interconnect structure in a semiconductor device in which via holes (62) defined in a dielectric layer are filled with a filler material (64), such as a porogen material, before a further dielectric layer (66) is deposited thereover. Trenches (72) are formed in the further dielectric layer and then the filler material exposed thereby in the via holes is removed. The method provides a robust process which affords improved via and trench profile control.

Abstract: A process (300) is disclosed to measure predetermined wavelength reflectance spectra of a photo resist coated wafer (305,310,315,320) at a nominal thickness. After coating, the predetermined wavelength reflectance (325,330) is measured and the peak heights and valleys in the vicinity of the predetermined wavelength are tabulated. The relative swing ratio is computed (335) as the average peak height of the spectra at the exposure wavelength. This relative swing ratio is then compared to similar computations on other processes to determine which provides the best critical dimension (CD) control.

Abstract: An electric device has an electrically switchable resistor (2?) comprising a phase change material. The resistance value of the resistor can be changed between at least two values by changing the phase of the phase change material within a part of the resistor called the switching zone (12?) using Joule heating of the resistor. The device comprises a body (24?) encapsulating the resistor, which body comprises at least two abutting regions (26?, 28?) having different thermally insulating properties. These regions form a thermally insulating contrast with which the dimension of the switching zone can be determined without having to alter the dimensions of the resistor. Such a device can be used in electronic memory or reconfigurable logic circuits.

Abstract: A receiver uses a sigma delta ADC (126) and an adaptable digital filter (132). Detector circuitry detects information about unwanted parts of the signal from an oversampled digital signal, before the filtering, and feeds forward the detected information to the filter, to adapt the filter. By feeding forward the detection information, rather than feeding back an output of the filter, the adaptation can respond much more quickly to rapid changes in the unwanted interference. This enables reduced filtering to save power when interference is low, without risking a sudden increase in interference causing an avalanche of errors before the filter can be adapted correctly. The filter receives the oversampled digital signal combines decimation and channel filtering in one stage.

Abstract: The present invention relates to a circuit configuration for detecting and rapidly limiting large current increase based on high current injection at the output terminal (out). In particular, a gate-controlled switching device (PO), controlled by a driver circuit (40) through a low resistive element (RO) and passed through by a current overshoot, will be alternatively driven by the circuit of the present invention while having its control terminal charged by the high injected current. Thus, when large voltage increase generated by a steep front impulse with a positive slope is detected by the capacitor (C) and transmitted to the gate terminal (GateN), the circuit of the present invention bypasses the driver circuit (40) while injecting a significant current peak issued from the transistor (P3) towards the gate terminal (GateP) of the gate-controlled switching device (PO), whereas the capacitor (C) is discharging very slowly through the gate terminal (GateN).

Abstract: An ESD protection circuit comprises a first supply line (VDD), a second supply line (VSS), an ESD protection device, preferably being configured as a transistor (MP), which is connected between the first and second supply line (VDD, VSS) and at least one pin (VA) connected to the first and second supply lines (VDD, VSS) via diodes D1, D2. The ESD protection device is controllable by a trigger voltage that is set by a trigger voltage setting circuit (RP, RD, Z1, Z2, Z3). The ESD protection circuit comprises a trigger circuit (1) being connected to the at least one pin (VA) and providing pin specific trigger voltages, wherein the trigger circuit (1) is further connected to the trigger voltage setting circuit.

Abstract: The present invention relates to an oscillator circuit and a method of controlling the oscillation frequency of an in-phase signal and a quadrature signal. First oscillator means (2) with a first differential oscillator circuit and a first differential coupling circuit are provided for generating the quadrature signal. Furthermore, second oscillator means (4) with a second differential oscillator circuit and a second differential coupling circuit are provided for generating the in-phase signal. A frequency control means is provided for varying the oscillation frequency of the in-phase signal and the quadrature signal by controlling at least one of a common-mode current and a tail current of the first and second oscillator means. Thereby, a high-frequency IQ oscillator with high linearity is obtained.

Abstract: A method for managing expired or consumed applications (app1, app2 . . . appx) that have been provided by a Service Provider (SP) and are stored in a memory element (SE) of a mobile communication device (MOB), e.g. a NFC mobile phone, comprises storing a representation (RP) of expired or consumed applications (app1, app2 . . . appx) in or on a storage medium that is separate from the memory element (SE).

Abstract: I2C clock generators are implemented using a variety of methods. Using one such method, a method is implemented using logic circuitry arranged in a state machine to control the clock signal (110) on the I2C bus. A first state (202) of the state machine determines whether to effect a clock stretching delay. A second state (206) of the state machine determines whether the I2C bus is configured to run in a standard clock mode or in another one of multiple faster clock modes. A third state (210) of the state machine drives the clock signal in one binary logic state for more than about 0.5 microseconds before allowing the clock signal (110) to be driven in the other binary logic state and allowing the clock signal to remain in the other binary logic state for more than about 0.5 microseconds.

Abstract: This invention relates to a star coupler connected to a plurality of nodes within a network using a time triggered protocol on a time slot basis. The invention further relates to a network including a cluster having at least one node. Further, the invention relates to a method for communication between nodes within a network using a time trigger protocol. To provide a star coupler, which is able to increase the bandwidth and to communicate with low propagation delay for communicating the relevant data it is proposed to provide a star coupler (11) comprising a switch (12) having a plurality of input branches and output branches, wherein a switch controller (13) is provided for controlling the switch (12), further comprising means (14, 15) for deriving knowledge about the protocol timing, which knowledge is used for selectively forward data in a certain time slot to at least one predetermined output.

Abstract: The present invention relates to a low noise amplifier comprising a transformer, a first amplifier and a feedback resistor, the transformer comprising a primary stage and a secondary stage. The secondary stage is connected to the input of the first amplifier and the output of the first amplifier is connected in series with a feedback resistor and the primary stage of said transformer.

Abstract: The present invention relates to a data storage unit for a communication system node, a method for data storage and a communication system node. More particularly it relates to storing buffering data and control data in a unit located outside of a Communication Controller on system or host-controller level, wherein a time-triggered protocol runs on the node. By locating control and buffering related data, including format and behaviour, outside the Communication Controller it becomes far more flexible, extendable, and re-configurable as data buffering related restrictions, e.g. buffer sizes and number of buffers, are moved from Communication Controller level to system level.

Abstract: A memory region protection unit is disclosed that comprises a first register for storing a memory region address, a second register for storing the memory region size, an arithmetic function block for executing an arithmetic function on a memory address provided to the region protection unit and the address value in the first register. The unit further has a comparator for comparing the output of the arithmetic function block with the size value in the second register, the comparator being coupled to an output for signalling the validity of the memory address on the bus The region protection unit has a controller configured to retrieve the memory region address and the memory region size from instructions issued to the region protection unit for associating the unit with said region, and to dissociate the unit from its memory region in response to a further instruction.

Abstract: A system, apparatus, and method are provided for using a PCB component as an antenna to allow for RFID communication in the UHF band. The present invention enables supply chain management of a PCB and products containing the PCB by enabling tracking of a PCB at the assembly level such that at each production stage of the board production it is known exactly where the product is and what is its present state of test. One embodiment uses an existing ground plane of a PCB, splitting the ground plane of all the layers of the PCB, allowing for a dipole structure that provides an adequate received energy level to power the circuit to the “on” state thereby allowing RFID/Electronic Product Code transactions. In alternative embodiments, existing or added traces are used in place of the split ground plane as an antenna for the RFID IC.

Abstract: In an example embodiment, there is a sensor for detecting particles. The sensor comprises an electrode, a sensor active region covering the electrode and the sensor active region is sensitive-for the particles. A first switch element is operable to bring the electrode to a first electric potential when the first switch element is closed, and a second switch element is operable to bring the electrode to a second electric potential when the second switch element is closed. A detector is adapted to detect the particles based on a change of the electric properties of the sensor in an operation mode in which the electrode is brought to the first electric potential and an operation mode in which the electrode is brought to the second electric potential.

Abstract: An integrated circuit (10) comprises a scan chain (14) with parallel inputs and outputs coupled to a functional circuit (12a-c). A scan chain modifying circuit (43, 47, 70a-c) is provided coupled to the scan chain (14). When testing is authorized the scan chain modifying circuit operates in a mode wherein a normal shift path is provided through the scan chain. When testing is not authorized the scan chain modifying circuit (43, 47, 70a-c) operates to effect spontaneous dynamic changes in the shift path, which dynamically vary the length of the shift path between external terminals of the integrated circuit while shifting takes place. In an embodiment the dynamical variations are controlled by a running key comparison. In other embodiments running key comparison is used to disable transfer through the scan chain and/or operation of functional circuits.

Abstract: A continuous-time sigma-delta analog-to-digital converter (CV) comprises i) a signal path (SP) comprising at least one combiner (C1) for combining analog signals to convert with feedback analog signals, at least two integrators (H1, H5), mounted in series, to integrate the combined analog signals, a quantizer (Q) for converting the integrated signals into digital signals, and a decimation filter (DF) for filtering digital signals, and ii) a feedback path (FP) comprising at least a digital-to-analog converter (DAC) for converting the digital signals output by the quantizer (Q) into feedback analog signals intended for the combiner (C1). Each integrator (H1, H5) comprises variable capacitance means arranged to be set in chosen states define by the values of a digital word, to present chosen capacitances.

Abstract: The invention provides a three-dimensional stacked fin metal oxide semiconductor (SF-MOS) device (10,30) comprising a protrusion or fin structure with a plurality of stacked semiconductor regions (3,5,12), in which a second semiconductor region (5,12) is separated from a first semiconductor region (3,5) by an isolation region (4,11). A gate isolation layer (8) extends at least over the sidewalls of the protrusion (7) and a gate electrode extends over the gate isolation layer (8). The gate electrode comprises a plurality of gate regions (13,14,15) wherein each gate region (13,14,15) extends over another semiconductor region (3,5,12). In this way each gate region (13,14,15) influences the conduction channel of another semiconductor region (3,5,12) and hence adds another degree of freedom with which the performance of the SF-MOS device (10,30) can be optimized. The invention further provides a method of manufacturing the SF-MOS device (10,30) according to the invention.

Abstract: Consistent with one example embodiment, a communications system uses an I2C serial data transfer bus that has a serial data line (110) and a clock line (120) used to implement a communications protocol. The communications system includes a slave device having address pins (400), each coupled to the serial data line, clock line, power line, or ground. Communications circuitry communicates with a master device in accordance with the communications protocol over the data transfer bus. Decoding circuitry detects a first state of the address pins (410), detects a second state of the address pins (420) subsequent to the detection of the first state, wherein one or more logic values of the address pins differ between the first state and the second state, and decodes a slave device address (430) as a functional relationship between the first state and the second state of the address pins.

Abstract: A communication station (1) and a transponder (2) are designed in such a way that an inventorizing operation can be performed using various memory areas (36, 37, 38, 39, 40), which are provided in an addressable memory (35) of the transponder (2), and in which different identification data (UIDDATA, USERDATA) is stored.