Abstract: A technique is provided for configuring and controlling complex hardware subsystems that relieves the burden placed on the system programmer and that is, by comparison to present methods, safe and error-free. In accordance with one aspect of the invention, configuration of a hardware subsystem (110) is accomplished by providing in hardware a configuration controller including a controller portion (113) and a storage portion (115) storing configuration parameters. The configuration controller (113) is activated, for example in response to a Configuration/Control ID, and thereupon performs configuration of the hardware subsystem (110), including storing at least one configuration parameter in a register (111) of the hardware subsystem. Typically, the configuration controller hardware (113) and storage (115) are embedded within the hardware subsystem to be configured or controlled.

Abstract: A cascode LNA circuit is provided with a tuned inductive load. The circuit shows a flat response over a wide frequency range.

Abstract: The integrated protection circuit according to the invention for ESD protecting an circuit device having at least one pad, e.g. a I/O pad, comprises a first transistor (MPI) whose control outputs are connected between the pad (2, 3) and the control input of a clamp transistor (MN4). The control outputs of the clamp transistor (MN4) are connected between the pad (2, 3) and a reference terminal (4). The protection circuit further comprises a second transistor (MN3) whose control outputs are connected between the control output of the first transistor (.MP 1) and the reference terminal (4). Finally the protection circuit also comprises time-delay elements (R, MN 1) connected between a supply voltage terminal (1) and the control inputs of the first transistor (MP I) and the second transistor (MN3).

Abstract: A transponder with an antenna and an antenna voltage limiting unit for limiting an antenna voltage to a first voltage limit when the transponder is receiving data and to a second voltage limit when the transponder is sending data. Dynamic voltage limitation may be implemented by using a computer program or implemented in hardware. Additionally, it is possible to introduce a third voltage limit when the transponder is in a third mode of operation such as standby or sleeping mode.

Abstract: A method of forming a Si strained layer 16 on a Si substrate 10 includes forming a first SiGe buffer layer 12 on the Si substrate 10. Then, the first SiGe buffer layer is implanted with an amorphising implant to render the first SiGe buffer layer amorphous using ion implantation. A second SiGe buffer layer 14 is grown on the first SiGe buffer layer after annealing. This produces a relaxed SiGe layer 12, 14. Then, the strained layer of Si 16 is grown.

Abstract: A data processing system is provided comprising at least one processing unit (PU) for data processing and a debugger means (DM) for debugging the processing of the at least one processing unit (PU) based on a plurality of breakpoints. The debugger means (DM) comprises a first register (BAR) for storing a base address for one of the plurality of breakpoints, wherein the debugging means (DM) initiates the debugging of the processing of the at least one processing units (PU) based on the base address stored in the first breakpoint register, i.e. the base address register. A second breakpoint register (OR) is provided for storing an offset for obtaining subsequent breakpoints. A logic arithmetic unit (LAU) is provided for repetitively calculating a breakpoint condition based on the base address stored in the first breakpoint register and the offset stored in the second breakpoint register and for updating the base address stored in the first breakpoint register.

Abstract: A plurality of digital signal processors (10), each contains a signal processing core (22), a memory (20) coupled to the processing core (22) and a multiplexed data input (16) coupled to the memory (20). Each digital signal processor has a plurality of outputs for outputting data from the signal processing core (22). A remote write only structure (14a-d) couples outputs of respective groups of the digital signal processors (10) each to the multiplexed data input (16) of respective particular digital signal processor (10), the respective group for the particular digital signal processor (10) not including the particular digital signal processor (10). Thus, each processor (10) writes data for other processors directly from the processor, without storing the data in memory first for handling by an I/O processor, and reads data from other processors (10) via memory, where it is received via an input that does not share resources with the output of the processor (10).

Abstract: A semiconductor device includes a semiconductor region having a pn junction and a field shaping region located adjacent the pn junction to increase the reverse breakdown voltage of the device. The field shaping region is coupled via capacitive voltage coupling regions to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction and the device is non-conducting, a capacitive electric field is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region. The electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region in the semiconductor region.

Abstract: A system for amplifying a digital audio signal comprises a receiver 12 for receiving a digital audio signal, a level estimator 14 arranged to calculate the audio level of the digital audio signal, a gain control 16 arranged to receive a gain level, the gain level defining the desired amplification of the digital audio signal, a logic circuit 18 arranged to calculate the headspace in the digital audio signal and to divide the gain level into a scaling gain and an amplifier gain, the scaling gain not exceeding the calculated headspace, a digital signal processor 20 arranged to amplify the digital audio signal with the scaling gain, a digital-to-analogue converter 22 arranged to convert the amplified digital audio signal into an analogue signal, and an amplifier 24 arranged to amplify the analogue audio signal with the amplifier gain.

Abstract: A membrane 103 for an acoustic device 100 is provided, the membrane 103, wherein the membrane 103 comprises a central portion 212, an annular portion 105, and a corrugation 107, wherein the annular portion 105 is arranged around the central portion 212, wherein the annular portion 105 is adapted to be fixed to a coil 106, and wherein the corrugation 107 is arranged between the central portion 212 and the annular portion 105. Thus, the corrugation 107 may form an inner corrugation compared to an outer corrugation 104 which would be arranged farther away from the central portion 212 than the annular portion 105.

Abstract: A method of decoding a digital video file comprising a plurality of encoded frames each having a first number of pixels, each encoded frame composed of an integer multiple of n-order square matrices, the method comprising: i) for each n-order square matrix, performing an inverse discrete cosine transformation on the n-order square matrix to produce an m-order square matrix, where m<n; ii) for each m-order square matrix, reducing the m-order square matrix to a p×m matrix, where p<m; iii) for each frame, producing a decoded frame composed of the integer multiple of p×m matrices derived from step ii), wherein each decoded frame has a second number of pixels smaller than the first number of pixels.

Abstract: A protection circuit (100, 700) is disclosed for protecting an integrated circuit having a first supply rail (Vcc) and a second supply rail (Vss) from exposure to an excessive voltage. The protection circuit (100, 700) comprises a sensor (120) for sensing a voltage increase on the first supply rail (Vcc). Such a sensor may be implemented as an RC element. The sensor (120) has an output coupled to a signal path for providing a detection signal on said path. The sensor (120) triggers a clamping circuit (180) to clamp the first supply rail (Vcc) to the second supply rail (Vss) in response to the detection signal, which typically signals an ESD event on the supply rails. A pre-amplifying stage (160) is coupled between the sensor (120) and the clamping circuit (180) to amplify the detection signal for the clamping circuit (180). The protection circuit further comprises a hold circuit (140) for holding the control input of the pre-amplifying stage (160) in an enabled state upon termination of the detection signal.

Abstract: This invention describes implementation of medium/high voltage semiconductor devices with a better voltage-blocking capability versus specific on-resistan?e trade off. This approach can be implemented in baseline and submicron CMOS without any additional process steps. Said devices comprise dielectric regions and semiconductor regions formed between them. Conductive extentions are formed on the dielectric regions, said extentions interacting capacitively with the semiconducter regions.

Abstract: Communication networks are implemented using a variety of devices and methods. In a particular embodiment for use in a communication network having RF-communication devices that communicate using a RF protocol, an RF-communication device is implemented with an RF transceiver (110) to communicate over the network using the RF protocol and being controllable in a reduced power-consumption mode in which the RF transceiver does not communicate over the network. The device also includes an RF receiver (104, 106) including an envelope detector (104) and a pulse generator circuit (106). The envelope detector circuit (104) providing an envelope-based signal to a pulse generator circuit (106) that, in response to the envelope-based signal and after generating a number of pulses that exceeds a predetermined number of pulses, prompts the RF transceiver (110) to transition out of the reduced power-consumption mode.

Abstract: A controller and a method for controlling lamp drivers such as e.g. LED drivers for lamps having a fast response behavior such as e.g. LED lamps are proposed. They enable to substantially reduce or prevent a visible luminance flicker at such lamps when dimming the lamps with a conventional dimmer such as e.g. a phase cut dimmer. This can be achieved by switching off the lamp driver prematurely in such a way that a time jitter of a dimmer switching does not influence an on-time of the lamp driver. No bulky or expensive filters or capacitors are needed. Thus, a space-switch saving and/or inexpensive construction is enabled.

Abstract: A module comprises a bus invert encoder (24) for determining whether a set of data bits should be inverted prior to transmission over a communication bus. The bus invert encoder (24) produces a bus invert signal BI which controls a selective inversion means (28), for example a multiplexer. A partial fault detection encoder (32) determines one or more temporary check bits from the set of data bits, substantially in parallel with the bus invert encoder (24). Thus, the one or more temporary check bits are determined based on the assumption that the set of data bits are to be transmitted without inversion from the selective inversion means (28). A logic unit (34) is provided for correcting the one or more temporary check bits, if necessary, based on the bus invert signal produced by the bus invert encoder (24).

Abstract: A system comprises at least one contactless readable data carrier (1) which can be attached to a wheel (100) of a vehicle and a reader (10) which can be arranged on the vehicle to receive electromagnetic signals (ES) emitted by the data carrier (1). The reader (10) is designed to determine the revolutions of the wheel (100) from the field strength fluctuation of the received electromagnetic signals (ES), the reader (10) having calculation means (19) designed to calculate from the revolutions and a wheel periphery reference value (RU) determined by the reader and allocated to the wheel (100), such as circumference, diameter or radius, a distance covered by a point on the wheel periphery and/or values derivable therefrom such as the peripheral speed (UV) of the wheel (100).

Abstract: An arrangement for navigation to predetermined destinations within a search area, which is divided up by means of a linear system of coordinates into coordinate fields, wherein, by means of automatic positioning at predetermined time intervals, that coordinate field is determined in which the arrangement is situated, wherein a database is provided which contains for each coordinate field a data record with a description of the current coordinate field and a description of the next coordinate field to be located in order to reach the destination, wherein the arrangement displays from the database to a user, who has input one of the predetermined destinations into the arrangement, the description of each new coordinate field as it is reached and the description of the next coordinate field provided for reaching the destination.

Abstract: In a signal processing circuit (3) for a contactlessly communicating communication partner device (1), there are provided a transmitted-signal path (9) and a received-signal path (10), the received-signal path (10) branching off from a branch point (AP) present on the transmitted-signal path (9), a filter stage (11) and a matching stage (12) connected downstream of the filter stage (11) being provided on the transmitted-signal path (9), the filter stage (11) having a resonant frequency that is in a frequency range the center frequency value of which matches an upper sideband frequency, and the branch point (AP) being situated between the filter stage (11) and the matching stage (12).

Abstract: A driver (Highside Driver, Lowside Driver) adapted to drive each of final transistors (MH, ML, Mpower) included in a power amplifier, the driver including: a first plurality of switches (Mpsiow, Mpmoderate, Mpfast) having their respective main current channels coupled between a bias voltage terminal (Vddx) and a control electrode of the respective final transistors (MH, ML, Mpower), said first plurality of switches (Mpsiow, Mpmoderate, Mpfast) being selectively turned ON for enabling a progressive charging of the respective control electrode of the final transistors (MH, ML, MPower), a second plurality of switches (Mnsiow, Mnfast) having their respective main current channels coupled between another bias voltage terminal (Vsource) and the control electrode of the respective final transistors (MH, ML, Mpower), said second plurality of switches (Mnsiow, Mnfast) being selectively switched ON until a current through the respective final transistors (MH, ML, Mpower) changes its polarity.