Abstract: The present invention relates to a circuit and a method for automatic common-mode rejection calibration in a differential conversion system and unbalance compensation for balancing the operation point of a circuit in the signal path and for enhancing the common-mode rejection.

Abstract: A leadframe structure (100) for an electronic package is provided, wherein the leadframe structure (100) comprises a die-pad (103), a barrier area (114), and a bonding area (111), wherein the barrier area (114) is arranged between the die-pad (103) and the bonding area (111), and wherein the barrier area (111) is adapted to electrically connect the die-pad (103) and the bonding area (111), and is further constructed in such a way that delamination growth between the leadframe structure (100) and a moulding compound fixable to the leadframe structure (100) is reduced.

Abstract: A memory device comprises an array of memory cells for storing data and a voltage application unit for applying voltages to the cells for writing data to the cells. Each memory cell has a first layer comprising copper in contact with a second layer comprising a chalcogenide material. The voltage application unit is arranged to write data by switching each cell between a first resistance state and a second, lower, resistance state. The voltage application unit is arranged to switch a cell to the first resistance state by applying a potential difference across the first and second layers such that the potential at the first layer is higher than the potential at the second layer by 0.5 volts or less. The voltage application unit is arranged to switch a cell to the second resistance state by applying a potential difference across the first and second layers such that the potential at the second layer is higher than the potential at the first layer by 0.5 volts or less.

Abstract: A non volatile memory device comprises memory cells such as MRAM cells, reading circuits and a reference cell for generating a reference for use by the reading circuits, and can determine if the reference is degraded by thermal instability. This can help reduce a data error rate. Detecting such degradation can prove to be more effective than trying to design in enough margins for the lifetime of the device. The reference cell can be less susceptible to degradation than other cells by using different shape of cells and different write currents. Where each reference cell is used by many memory cells, the reference cell tends to be used more often than any particular memory cell and so can be more susceptible to degradation. Another way of ensuring against longer term degradation of the reference is periodically rewriting the reference cell.

Abstract: A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.

Abstract: An electronic device comprising at least one input/output circuit (10) in a first supply voltage domain (VDD, GND) is provided. The electronic device furthermore comprises a buffer (INV) which is coupled to the input/output circuit for driving an input of the input/output circuit (10). The buffer comprises a first and second switch (T1, T2; T4, T5). The buffer is arranged in a second supply voltage domain (VDD1, GND1). Furthermore, a control circuit is coupled to the buffer for controlling the first and second switch (T1, T2; T4, T5) such that during a transition of an input signal of the input/output circuit (10) both switches (T1, T2; T4, T5) are temporarily kept in a conducting state and a crowbar current flows through the buffer (INV).

Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate identification of inter-integrated circuit slave devices using device identification coding. The communications system includes a slave device having a device identification code identifying one or more parameters. Communications circuitry in the slave device is configured to communicate with a master device on the I2C serial data transfer bus using the communications protocol. In response to a transmission of a device identification address from the master device, the slave device is configured to transmit an ACKNOWLEDGE, and in response to a transmission of a slave device address and the device identification address from the master device, the slave device is configured to transmit the device identification code from the slave device to the master.

Abstract: There is a method of manufacturing a semiconductor device with a semiconductor body comprising a semiconductor substrate and a semiconductor region which are separated from each other with an electrically insulating layer which includes a first and a second sub-layer which, viewed in projection, are adjacent to one another, wherein the first sub-layer has a smaller thickness than the second sub-layer, and wherein, in a first sub-region of the semiconductor region lying above the first sub-layer, at least one digital semiconductor element is formed and, in a second sub-region of the semiconductor region lying above the second sub-layer, at least one analog semiconductor element is formed. According to an example embodiment, the second sub-layer is formed in that the lower border thereof is recessed in the semiconductor body in relation to the lower border of the first sub-layer Fully depleted SOI devices are thus formed.

Abstract: A method of providing a region of doped semiconductor (40) which is buried below the surface of a semiconductor substrate (10) without the requirement of epitaxially deposited layers is provided. The method includes the steps of forming first and second trench portions (26,28) in a semiconductor substrate and then introducing dopant (100) into the trench portions and diffusing the dopant into the semiconductor substrate such that a region of doped semiconductor (40) is formed extending from the first trench portion to the second trench portion. A diffusion barrier, for example formed of two barrier trenches (16, 18), is provided in the substrate adjacent the doping trenches to inhibit lateral diffusion of dopant from the doping trenches so as to maintain an undoped region (30) above the region of doped semiconductor.

Abstract: An electro-acoustic transducer (1) is disclosed, comprising a substrate (2) that comprises conducting paths (3), a cover (4) attached to said substrate (2) thus forming an inner chamber (A) and a space (B) outside said chamber (A), wherein said cover (4) comprises one or more ports (5). A MEMS sensor (6) of said transducer (1) has at least one hole (7) extending from a first side (C) to a second side (D). A membrane (8) is arranged in said hole (7) transverse to the hole axis (E) thus forming a first hole space (a) and a second hole space (b). The sensor (6) furthermore has electrical connectors (9) designed to carry electrical signals representing sound acting on said membrane (8), which connectors (9) are connected to said conducting paths (3). According to the invention, said MEMS sensor (6) is arranged inside said chamber (A) in such a way that said second hole space (b) is connected to said outside space (B) via said port or ports (5) and said first hole space (a) is connected to said inner chamber (A).

Abstract: A road toll system comprises a vehicle-mounted unit having a satellite navigation receiver. A first data processing means determines a route taken 5 based on satellite navigation data provided from the receiver, and the satellite navigation data is associated with a variable identity. A road toll level is derived. A second data processing means receives the road toll level provided by the first data processing means, and the satellite navigation obtains the determined road toll level from the second data processing means using the 10 variable identity. This provides a thin client scenario (the receiver does not implement the map calculations), but with data security corresponding to a thick client solution. Thus, the map matching and trip cost computation steps are delegated by the on-board unit to an external unit, but this delegation is performed anonymously, so that no data sent for external processing 15 compromises the privacy of the data.

Abstract: A system 100 for securely storing digital data includes a data storage 110 and a physical uncloneable function 120 (PUF), including an input (122) for receiving a challenge and an output (124) for producing a response to the challenge. Means 130 determine an identifier associated with the data storage. Means 140 supply a representation of the identifier to the PUF as a challenge and retrieve a corresponding response from the PUF. A cryptographic unit 150 performs a cryptographic operation for securing or verifying a digital content item stored in the data storage, where the cryptographic operation is performed under control of a cryptographic key derived from the received response.

Abstract: A secure computing device (100) includes a secure cryptographic module (120) with a key generation unit (124) for generating a cryptographic key in dependence on received input. A storage (140) is used for storing a virtual machine (142) that is executable on a processor (110) and at least one program (144) that is executable on the virtual machine. A virtual machine manager (130) including means 132 for determining an identifier associated 5 with the virtual machine, means 134 for supplying a representation of the identifier to the secure cryptographic module and retrieving a cryptographic key from the secure cryptographic module; and means 136 for, under control of the cryptographic key, decrypting at least a part of data input to the processor and encrypting at least part of data output from the processor when the processor executes the virtual machine.

Abstract: A mobile communication device (1) is connectable to a classic or emulated MIFARE memory (MM) and comprises a MIFARE applications manager (MAM) which parses the MIFARE memory (MM) for parts of the memory being occupied by MIFARE applications and for empty memory spaces between the occupied parts of the memory. If a predefined number or size of empty memory spaces is detected, the MIFARE applications manager (MIFARE applications manager) does a de-fragmentation of the MIFARE memory (MM) by reorganizing the storage location of MIFARE applications so that they are arranged close together, preferably arranged contiguously.

Abstract: A cable management device (110), the cable management device (110) comprising a casing (111) having a first guiding opening (112) through which a first cable (114) connected to a first electric member (116) is guidable, having a second guiding opening (113) through which a second cable (115) connected to a second electric member (117) is guidable, and having an accommodation chamber (400) for accommodating at least the first electric member (116), and a cover element (118) being movably mounted on the casing (111) to selectively expose or cover the accommodation chamber (400).

Abstract: Arrangement for accepting an input signal in a first voltage range and producing an output signal in a second voltage range. A transition detection circuit (230) detects a transition from a high level to a low level of the input signal and a control circuit (245) operates a first FET to produce the low level of the output signal. A second FET is operated by the high level of the input signal to output the high level of the output signal.

Abstract: Disclosed are methods and circuits for detecting and recording timestamps for multiple events (222/322, 224/324) using a single input pin (252, 352) on a real time clock (RTC) (250, 350). Signals associated with each of the events are modulated to create a multiple level composite signal (240). The RTC includes a multiple signal level detection circuit to distinguish from among the various signal levels so that each event can be separately flagged and timestamped. For example, the opening of two or more covers (112, 114) on the housing (110) of an electronic device (100) can be monitored, distinguished, and separately flagged using a single RTC input port.

Abstract: The invention provides a LED arrangement including a LED string of a series arrangement of LED segments. A LED segment includes a single LED or a series arrangement of LEDs. A switching element (12, 22) is arranged in parallel with each corresponding LED segment (10, 20) of the LED string, for controlling a current (52, 62) through the LED segment (10, 20). A capacitor (13, 23) is arranged in parallel with each corresponding LED segment (10, 20) in order to prevent the occurrence of possibly harmful current spikes while switching one or more LED segments. The LED arrangement may also include a switched-mode power supply (2001). The invention further provides a LED assembly. A plurality of such LED assemblies assembles easily into a LED arrangement according to the invention.

Abstract: A sensor senses a characteristic of an environment, e.g., humidity. The sensor has a substrate with strips of material that is sensitive to corrosion as a result of the characteristic. The strips are configured to respond differently to the characteristic. By means of repeatedly measuring the resistances of the strips, the environment can be monitored in terms of accumulated exposure to the characteristic. The strips are manufactured in a semiconductor technology so as to generate accurate sensors that behave predictably.

Abstract: A magnetoresistive sensor system (400) is provided, wherein the system comprises a magnetic field source (402), a magnetoresistive sensor (403) having an easy axis, and a differentiation element (404), wherein the magnetic field source (402) is adapted to emit an auxiliary magnetic field generated from an oscillating input signal (401), wherein the auxiliary magnetic field is orthogonal to the easy axis of the magnetoresistive sensor (403), wherein the magnetoresistive sensor (403.) is adapted to sense a signal associated to a superposition of an external magnetic field and the auxiliary alternating magnetic field, and wherein the differentiation element (404) is adapted to differentiate the sensed signal.