Patents Assigned to NXP
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Publication number: 20100146535Abstract: A method and a device (1) for deterring children and adolescents from using an audio and/or audiovisual device (1), especially a TV set or a radio, while censored programs (X-Prog) are played by said device (1), said method comprising outputting an annoyance audio signal (AN) from the audio and/or audiovisual device (1) simultaneously with the censored program (X-Prog), wherein the annoyance audio signal (AN) has a frequency that can be heard by children and adolescents but is above the hearing threshold of adults.Type: ApplicationFiled: May 5, 2008Publication date: June 10, 2010Applicant: NXP B.V.Inventor: Stefan Wieser
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Publication number: 20100146641Abstract: Data, stored in MRAM-cells should be protected against misuse or read-out by unauthorised persons. The present invention provides an array of MRAM-cells provided with a security device for destroying data stored in the MRAM-cells when they are tampered with. This is achieved by placing a permanent magnet adjacent the MRAM-array in combination with a soft-magnetic flux-closing layer. As long as the soft-magnetic layer is present, the magnetic field lines from the permanent magnet are deviated and flow through this soft-magnetic layer. When somebody is tampering with the MRAM-array, e.g. by means of reverse engineering, and the flux-closing layer is removed, the flux is no longer deviated and affects the nearby MRAM-array, thus destroying the data stored in the MRAM-cells.Type: ApplicationFiled: February 19, 2010Publication date: June 10, 2010Applicant: NXP B.V.Inventors: Kars-Michiel Hubert Lenssen, Robert Jochemsen
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Publication number: 20100141668Abstract: The invention relates to a address calculation unit (15) for region based image processing tasks, where a processing unit (15) processes the data and exchanges the processed data between a global memory (11) and a local memory (12), wherein the address calculation of region-based algorithms is performed by the address calculation unit in parallel to the date processing of the and the actual processing of data.Type: ApplicationFiled: October 5, 2007Publication date: June 10, 2010Applicant: NXP, B.V.Inventors: Winfried Gehrke, Thomas Hinz
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Publication number: 20100139526Abstract: A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device.Type: ApplicationFiled: February 12, 2010Publication date: June 10, 2010Applicant: NXP B.V.Inventors: Janos FARKAS, Srdjan KORDIC, Cindy GOLBERG
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Patent number: 7733729Abstract: A non volatile memory device comprises memory cells such as MRAM cells, reading circuits and a reference cell for generating a reference for use by the reading circuits, and can determine if the reference is degraded by thermal instability. This can help reduce a data error rate. Detecting such degradation can prove to be more effective than trying to design in enough margins for the lifetime of the device. The reference cell can be less susceptible to degradation than other cells by using different shape of cells and different write currents. Where each reference cell is used by many memory cells, the reference cell tends to be used more often than any particular memory cell and so can be more susceptible to degradation. Another way of ensuring against longer term degradation of the reference is periodically rewriting the reference cell.Type: GrantFiled: March 29, 2005Date of Patent: June 8, 2010Assignee: NXP B.V.Inventor: Hans Marc Bert Boeve
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Patent number: 7734261Abstract: The object of the invention, which relates to a method and an arrangement for calibrating an analog I/Q modulator in a high-frequency transmitter, is to provide a method and an associated circuit arrangement by means of which a calibration of the I/Q modulator is carried out without a balancing operation and thus the complexity is minimized.Type: GrantFiled: December 9, 2005Date of Patent: June 8, 2010Assignee: NXP B.V.Inventor: Andreas Bury
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Patent number: 7733142Abstract: Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.Type: GrantFiled: February 24, 2006Date of Patent: June 8, 2010Assignee: NXP B.V.Inventors: Alma Anderson, Joseph Rutkowski, Dave Oehler
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Patent number: 7733657Abstract: In a module base unit (1) for a module (30) for a data carrier, two connection plates (2, 3) are provided, which comprise electrically conductive material and which each have a direction of extent (4, 5) and which are separated from each other by a gap (16) transverse to the two directions of extent (4, 5), and at least one strain relief member (34) is connected to the two connection plates (2, 3), which strain relief member (34) is constructed to absorb tensile forces occurring parallel to the directions of extent (4, 5) and acting on the connection plates (2, 3).Type: GrantFiled: July 26, 2005Date of Patent: June 8, 2010Assignee: NXP B.V.Inventors: Reinhard Fritz, Gerald Schaffler, Joachim Schober
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Patent number: 7733940Abstract: The present invention provides for a method of receiving a signal spread over a frequency range, and in particular a direct sequence spread spectrum signals including the step of employing a Fast Fourier Transform (FFT) in the Doppler search. In particular, the invention relates to the receipt of spread spectrum signals such as those transmitted as part of a GPS system.Type: GrantFiled: December 13, 2002Date of Patent: June 8, 2010Assignee: NXP B.V.Inventors: Saul R. Dooley, Amites Sarkar, Andrew T. Yule
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Publication number: 20100138890Abstract: The invention relates to an electronic device for processing input stream data including capturing, watching, digitising compressing, storing and/or analysing analogue or digital stream data consisting of at least one TV tuner and an encoder or a decoder, wherein the encoder or the decoder comprises a terminal or pin providing data of a content analysis.Type: ApplicationFiled: April 24, 2008Publication date: June 3, 2010Applicant: NXP B.V.Inventor: Olaf Seupel
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Publication number: 20100138839Abstract: A multiprocessing system executes a plurality of processes concurrently. A process execution circuit (10) issues requests to access a shared resource (16) from the processes. A shared access circuit (14) sequences conflicting ones of the requests. A simulating access circuit (12) generates signals to stall at least one of the processes at simulated stall time points selected as a predetermined function of requests from only the at least one of the processes and/or the timing of the requests from only the at least one of the processes, irrespective of whether said stalling is made necessary by sequencing of conflicting ones of the requests. Thus, part from predetermined maximum response times, predetermined average timing can be guaranteed, independent of the combination of processes that is executed.Type: ApplicationFiled: March 26, 2008Publication date: June 3, 2010Applicant: NXP, B.V.Inventors: Marco J. G. Bekooij, Jan W. Van Den Brand
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Publication number: 20100134205Abstract: The present invention relates to a tunable filter device for providing a tunable band pass characteristics for the receive path of a multi-band front-end module. According to the invention is proposed, a distributed, wide-band amplifier with a low-frequency cut-off and a high-frequency cut-off in combination with a LCR network, of which wide-band amplifier the DC blocking capacitors define the low-frequency cut-off of the filter device, whilst the high-frequency cut-off is determined by the cut-off frequency of the artificial input and output transmission lines of the LCR network. In one embodiment, additional capacitors are coupled in parallel to the DC blocking capacitors of the LCR network, switchable by MOS transistors as switching elements. Accordingly, in a certain embodiment it is proposed to allow tuning of the low- and the high-frequency cut-off by programming with a digital control command.Type: ApplicationFiled: April 24, 2008Publication date: June 3, 2010Applicant: NXP B.V.Inventor: Patrice Gamand
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Publication number: 20100138669Abstract: It is described a method for encrypting and a method for decrypting at least a portion (155) of a dataset being stored in a memory (150), wherein the dataset has at least two dimensions. The described multi-dimensional cryptographic methods comprise forming a first keystream (165) being assigned to a first dimension of the dataset and forming a second keystream (175) being assigned to a second dimension of the dataset The encrypting method further comprises encrypting each data packet of the portion (155) of the dataset by using a combination of the first keystream (165) and the second keystream (175). The decrypting method further comprises decrypting each data packet of the portion (155) of the dataset by using a combination of the first keystream (165) and the second keystream (175).Type: ApplicationFiled: March 11, 2008Publication date: June 3, 2010Applicant: NXP, B.V.Inventors: Klaus Kursawe, Timothy Kerins
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Publication number: 20100135414Abstract: The present invention relates to a video decoder (DEC) for decoding a bit stream (BS) corresponding to pictures (P) of a video signal, coded pictures being likely to include macroblocks coded in a progressive and in an interlaced way, said decoder including a decoding unit (DEU) for decoding macroblocks coded in a progressive way. A video decoder according to the invention includes a decoding configuration unit (DCU) for activating said decoding unit several times for decoding a single picture and for configuring the read and/or write stride at each pass of said picture in said decoding unit.Type: ApplicationFiled: May 30, 2006Publication date: June 3, 2010Applicant: NXP B.V.Inventor: Stephane Valente
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Publication number: 20100135394Abstract: The present invention relates to a video decoder (DEC) for decoding a bit stream (BS) corresponding to pictures (FR) of a video signal. The invention is such that, motion vectors (MV1) having values coded at a nominal resolution in the bit stream, said video decoder includes a rounding unit (RND) for rounding decoded nominal motion vectors (MV1) to a resolution different from the nominal resolution in a way that minimizes the error accumulation along prediction path by giving to rounded successive motion vectors (MV2) along the prediction path, successive values such that their average value is equal to the value of the nominal motion vector.Type: ApplicationFiled: June 7, 2006Publication date: June 3, 2010Applicant: NXP B.V.Inventors: Stephane Valente, Nicolas Vanhaelewyn
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Publication number: 20100134255Abstract: In an RFID system an RFID device (2) comprises a device air interface (C2) with a predefined quality factor (Q2) for transmitting wireless carrier and data signals (CS) being transmitted to a remote RFID transponder(1) comprising a transponder air interface (C1) with a predefined quality factor (Q1). Carrier and data signal pre-compensation means (3) are arranged between the device air interface (C2) and data signal processing means (4), wherein the carrier and data signal pre-compensation means (3) are adapted to pre-compensate signal distortions of the carrier and data signals (CS) caused by the quality factors (Q2, Q1) of the device air interface (C2) and the transponder air interface (C1) of the RFID device (2) and the RFID transponder(1), respectively.Type: ApplicationFiled: May 27, 2008Publication date: June 3, 2010Applicant: NXP B.V.Inventor: Harald Witsching
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Patent number: 7728404Abstract: A semiconductor device includes a substrate of a first conductivity type, and a first semiconductor region that includes a plurality of sub-regions of the first conductivity type that have a first doping concentration and a further semiconductor region of a second conductivity type opposite to the first conductivity type. The further semiconductor region separates the sub-regions from each other and the first semiconductor region is located on the substrate. The semiconductor device further includes a second semiconductor region of the first conductivity type located on the first semiconductor region, a third semiconductor region of the second conductivity type located on the second semiconductor region, and a fourth semiconductor region of the first conductivity type located on the third semiconductor region.Type: GrantFiled: September 26, 2008Date of Patent: June 1, 2010Assignee: NXP B.V.Inventors: Rob Van Dalen, Gerrit Elbert Johannes Koops
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Patent number: 7726011Abstract: In a chip transferring apparatus a wafer (44) and a lead frame (50) are positioned. A first chip (42) is picked up from the wafer (44) by a transfer head (14; 40a-40d) in a chip pick-up position, while bonding a second chip to the lead frame (50) by another transfer head in a chip bonding position. The first chip (42) is then transferred by said one of the transfer heads from the chip pick-up position to the chip bonding position. Next, the first chip (42) is bonded on the lead frame (50) by said one of the transfer heads (14; 40a-40d) in the chip bonding position, while another one of the transfer heads picks up a third chip from the wafer (44) in the chip pick-up position. Each transfer head (14; 40a-40d) comprises a collet (66a-66d) which, through a mechanical coupling, is coupled to another collet for compensating radial forces exerted on the collet relative to said axis of rotation.Type: GrantFiled: December 11, 2003Date of Patent: June 1, 2010Assignee: NXP B.V.Inventors: Johannes Wilhelmus Dorotheus Bosch, Wilhelmus Johannus Theodorus Derks, Antonius Hendrikus Jozef Kamphuis, Thomas Markus Kampschreur, Joep Stokkermans, Leon Wetzels
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Patent number: 7729410Abstract: A system for and method of converting successive bits of digital data into BPSK symbols using one or more BPSK symbol constellations such that orthogonal BPSK constellations are referenced to successive bits of the digital data. The system and method may toggle between referencing first and second orthogonal constellations as successive bits of the digital data are encountered. Alternatively, the system and method may successively rotate by 90° the constellation to be referenced as successive bits of the digital data are encountered. The reversal of the systems and methods described can be used to decode a transmission made by the methods described or specifically to reference a succession of orthogonal BPSK constellations to convert a succession of BPSK symbols to a succession of bits of digital data. Furthermore, a standard quadrature receiver can be used to perform the conversion.Type: GrantFiled: March 31, 2008Date of Patent: June 1, 2010Assignee: NXP B.V.Inventor: Donald Brian Eidson
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Patent number: 7728754Abstract: An integrating analog to digital converter (ADC) is disclosed that comprises a Delay Locked Loop (DLL) (2, 50) which is synchronized to a reference clock signal (12). A rising edge of a clock signal therefore propagates through the DLL once each clock cycle. In use, the integrating ADC converts an analog input signal to a digital output signal dependent upon a timing measurement of an integration carried out by an integrator (4). The timing measurement is taken by reading the logical states of the individual delay cells in the DLL. This enables the position of the rising edges of the clock signal to be determined and used as a timing measurement. The timing measurement is in the form of a digital thermometer code that can be converted into a binary number.Type: GrantFiled: November 8, 2006Date of Patent: June 1, 2010Assignee: NXP B.V.Inventors: Friedel Gerfers, Wolfgang Furtner
