Abstract: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).

Abstract: The present invention relates to a circuit arrangement and method of controlling power consumption of the circuit arrangement, wherein a load applied at a circuit component is determined and the drive capacity of the circuit component is adjusted responsive to the determination result. In particular, the circuit component is tailored to have just sufficient drive capacity depending on the potential load which may be determined by examining a configuration information loaded to the circuit arrangement. Tailoring for sufficient drive can be achieved either by varying the size or number of circuit components or by adjusting the threshold voltage of circuit elements, or by doing both. Thereby, power consumption can be reduced when circuit components are driven at loads lower than the worst case load.

Abstract: A security subsystem controls the data transfer rights among components of a secured system via a common bus. The security subsystem includes a secure block that is coupled to an access controller, preferably via a hard-wired connection to the controller. This secure block exclusively controls the access rights among components, and can effectively isolate security functions and data from the main processor. Because the security is provided via access control to components or subsets of components via a common bus, an efficient and effective integration of the security subsystem within the secured system can be achieved.

Abstract: An electronic circuit is provided comprising an input (VIN) for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage (VDD) and a voltage (VSS). The third transistor (M1) is coupled between the voltage (VSS) and a first node (tn). The second transistor (M2) is coupled between a second node (tp) and the output (VOUT). The third transistor (M3) is coupled between the first node (tn) and the output (VOUT). The fourth transistor (M4) is coupled between the supply voltage (VDD) and the second node (tp). A first reference voltage generating unit (RC) receives the voltage at the first node (tn) and the voltage (VSS) as input, and its output is coupled to the gate of the second transistor (M2). A second reference voltage generating unit (RD) receives the supply voltage (VDD) and the voltage of the second node (tp) as input, and its output is coupled to the gate of the third transistor (M3).

Abstract: The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion (2) on a substrate (1), a first layer (3) and a second layer (4) are formed, after which the top surface of the protrusion (2) is exposed. A portion of the first layer (3) is selectively removed relative to the protrusion (2) and the second layer (4), thereby creating a fin (6) and a trench (5). Also a method is presented to form a plurality of fins (6) and trenches (5). The dual-gate FET is created by forming a gate electrode (7) in the trench(es) (5) and a source and drain region. Further a method is presented to fabricate an extremely short-length asymmetric dual-gate FET with two gate electrodes that can be biased separately.

Abstract: A technique for performing data encryption for a cryptographic system that utilizes a cyclic group having an order is disclosed. The technique involves encoding a secret key into an encoded secret key using an encoding key, where the secret key and the product of the encoding key and the encoded secret key are congruent modulo the order of the cyclic group, serially encrypting a message into an encrypted message using the encoded secret key and the encoding key, and transmitting the encrypted message to a destination.

Abstract: A communication device (1, 1?, 1?) with at least one wireless communication channel is configured to receive digital pictures and/or video streams from at least one remote source. The communication device (1, 1?, 1?) is configured to test whether at least one person who is/are associated with said communication device by pre-stored person identification data is identifiable in the digital pictures and/or video streams of the remote source, and to process the digital pictures and/or video streams of the remote source only if the result of the person identification test is positive.

Abstract: Radio-frequency (RF) circuits, methods and systems are implemented according to a variety of embodiments. According to one such embodiment, a radio-frequency (RF) receiver circuit is implemented with an adjustable RF filter circuit in a receive path of the RF receiver circuit. A local oscillator (LO) generates a LO signal and an RX_LO signal from the LO signal. A mixing circuit mixes a signal received from the adjustable RF filter circuit and the RX_LO signal. An intermediate-frequency (IF) circuit generates an IF_cal signal at the receiver circuit. A calibration circuit implements both a calibration mode and a receive mode. In the calibration mode, a calibration signal is injected into the receive path. A setting of the adjustable RF filter circuit is determined. In the receive mode, the calibration circuit disables the injection of the calibration signal into the receive path of the RF receiver circuit.

Abstract: An electronic device (2) is made from a first substrate (22) with device circuitry (32) including an inductor (42) and a second substrate (24) with inductance adjustment circuitry (60) including a number of other inductors (62). The substrates (22, 24) are assembled together to be opposite one another. The other inductors (62) are arranged to provide a selection of different mutual inductance relationships relative to the inductor (42). These relationships are selectable during operation of the device to provide a variable inductance in the device circuitry (32).

Abstract: The present invention relates to a circuit arrangement and method of applying predistortion to a baseband signal used for modulating a pulse-shaped signal, wherein an envelope information of the baseband signal is detected and slewing distortions of the pulse-shaped signal are reduced by applying at least one of a phase modulation and a duty cycle 5 modulation to the baseband signal as additional predistortion in response to the detected envelope information. Thereby, slewing distortions in the pulse-shaped signal are removed or at least reduced.

Abstract: The present invention relates to a signal processing apparatus comprising a signal input and a signal output; a plurality of signal processing units, wherein each signal processing unit having the same structure and at least one spatial error, being connected to the signal input, and being adapted to subject an input signal from the signal input to predetermined signal processing; selection means configured to select and form a predetermined number of groups from the plurality of signal processing units in accordance with a predetermined criterion; and control means for controlling the groups of the signal processing units to be active in a time interleaved schema, wherein an active group provides a respective processed input signal as an output signal to the signal output; wherein the plurality of signal processing units comprises more signal processing units as required to realize a predetermined time interleaving factor.

Abstract: In an example embodiment, an integrated circuit comprises a mixer circuit and a local oscillator circuit. During testing a frequency divider circuit in the integrated circuit divides a local oscillator signal to a frequency below a normal operating range of the local oscillator. The integrated circuit applies the divided local oscillator signal to the mixer circuit instead of the local oscillator signal during testing. Signal properties of a signal derived from the mixer circuit are measured while the divided local oscillator signal is applied to the mixer circuit.

Abstract: The invention relates to FETs with stripe cells (6). Some of the cells have alternating low and high threshold regions (10, 8) along their length. In a linear operations regime, the low threshold regions conduct preferentially and increase the current density, thereby reducing the risk of thermal runaway. By distributing the low threshold regions (10) along the length of the cells (6), the risk of current crowding is reduced.

Abstract: A method recognizes whether a transponder designed for communicating with a communication station belongs to one of at least two groups of transponders. First, for each group of transponders, a check data block that is significant for the group of transponders is generated. Then, the data from the check data block that is significant for the group of transponders is evaluated for the recognition of whether the transponder belongs to the group of transponders.

Abstract: A flash analog-to-digital converter comprising a resistive reference ladder, a set of comparators for comparing the analog input signal with the reference voltages of the ladder to provide a digital code representing a coarse quantization of the input signal, a set of switches connected to the reference ladder and controlled by said digital code to provide an analog representation of the coarse quantization of the input signal, means to derive from said analog representation of the coarse quantization and from the input signal one or more residue signals and a fine analog-to-digital converter stage to generate a digital code representing a fine quantization of the one or more residue signals.

Abstract: In order to provide a circuit arrangement (100; 100?; 100?) for use in a data transmission system comprising at least one input stage (IS) being connected downstream of at least one bus system (CB), in particular of at least one C[ontroller]A[rea]N[etwork] bus system, the input stage (IS) comprising at least one resistive ladder (RL) for dividing the input signals; and at least one amplifier stage (AS) connected downstream of the input stage (IS), as well as a corresponding method with improved common mode range and with better H[igh]F[requency] performance, it is proposed that that the voltage range of the amplifier stage (AS) is limitated to a defined maximum voltage, in particular to the supply voltage (VCC).

Abstract: In a lateral thin-film Silicon-On-Insulator (SOI) device, a field plate is provided to extend substantially over a lateral drift region to protect the device from package and surface charge effects. In particular, the field plate comprises a layer of plural metallic regions which are isolated laterally from one another by spacing so as to assume a lateral electric field profile which is established by a volume doping gradient in the silicon drift region.

Abstract: The invention relates to a resistor network (2) such as a resistor ladder network, comprising at least a resistor body (4) which is provided with at least a column (6) of taps (8) situated between a first tap and a second tap, wherein, in use, at least two taps can be connected with respective first and second sources of reference input potentials, and wherein each tap of the at least one column of taps can be used for outputting an output potential via a contact area which is connected with the concerning tap, wherein the resistor body (4) comprises a multiple of resistor sub-bodies (5), wherein each resistor sub-body (5) is connected with a column (6) of taps (8), and wherein the only electrical connections between the resistor sub-bodies (5) are established by electrical connections via taps (8) connected with the resistor sub-bodies (5). Furthermore the invention relates to a method for manufacturing a resistor network (2) such as a resistor ladder network.

Abstract: An input signal is compared to 2N?1 reference voltages to generate 2N?1 corresponding binary valued comparison signals, delaying at least one of the comparison signals by a variable delay and detecting a difference in arrival time between the delayed signal and another comparison signal. A time interpolation signal encoding a plurality of bins within a least significant bit quantization level is generated, based on the detected difference in arrival time. An M-bit output data is generated based on the comparison signals and the time interpolation signal. A non-uniformity of a code density of the M-bit output data is detected, and based on the detecting the delaying is varied.

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a plurality of integrated circuits (1a, 1b, 1c) formed on the wafer substrate (2). Each integrated circuit (1a, 1b, 1c) comprises an electric circuit (24) and some of the integrated circuits (1b, 1c) comprise, in addition to their electric circuits (24), process control modules (3) as integral parts. The process control modules (3) are employed during dicing and pick-and-place to align the dicing/pick-and-place devices.