Abstract: The present invention discloses a vertical phase-change-memory (PCM) cell, comprising a stack of a bottom electrode (5) contacting a first layer of phase change material (14), a dielectric layer (12) having an opening (13), a second layer of phase change material (6) in contact with the first layer of phase change material through the opening in the dielectric layer and a top electrode (7) contacting this second layer of phase change material.

Abstract: A pulse-width modulation (PWM) amplifier comprises a feedback loop for reshaping the pulses of the PWM input signal to correct timing and amplitude errors in the class D output stage of the amplifier by means of an error correction signal. In such an amplifier the feedback loop gives a substantial amount of base-band noise when the pulse-period of the PWM input signal is not constant, which is especially the case when the PWM signal originates from a noise shaper. The invention reduces this noise by modifying the reshaping gain of the amplifier with a pulse-period proportional signal.

Abstract: A microelectronic package (31) has a microelectronic device, which is encapsulated in a quantity of material (27), and a lead frame element (15) for enabling the microelectronic device to be electrically contacted from outside of the package (31). The lead frame element (15) comprises at least two elongated members (11) comprising electrically conductive material and a filling material (12) comprising electrically insulating material, wherein the members (11) are partially embedded in the filling material (12). The lead frame element (15) is manufactured by providing elongated members (11), positioning the members (11) according to a predetermined configuration, providing filling material (12) to spaces (13) which are present between the members (11), and possibly removing portions of the filling material (12) and the members (11) in order to expose the electrically conductive material of the members (11).

Abstract: A BiCMOS substrate includes a bipolar area having a buried carrier layer, and a deep trench isolation (DTI) trench extending into the buried carrier layer to form a surface well implant above a buried well implant within the DTI trench, the buried well implant being the buried carrier layer portion within the DTI trench. A floating gate is disposed on the carrier well. Optionally, a high voltage control gate is formed of a stack of the buried well implant and the surface well implant within the DTI trench. Optionally, a poly layer formed of a bipolar process base poly layer is disposed on the floating gate. Optionally, a shallow well isolation region is formed on the substrate, a floating gate is disposed on the shallow well region, and an overlaying control gate, formed of a bipolar process base poly, is disposed above the floating gate.

Abstract: A method to track and control the resonance frequency of a band-pass filter provides a solution for the sensitivity limitations against temperature and process variations. A phase sensing module obtains the phase difference between the input and output and a negative feed-back control architecture can be used to tune the filter's resonance over the input RF frequency.

Abstract: A tuner is disclosed which overcomes a problem related to leakage currents within a tuner associated with increased miniaturization. The tuner includes an oscillator and a cover. The cover includes a barrier region, typically in the form of a slot or an air gap, which impedes the propagation of leakage currents, in the form of eddy currents induced from the oscillator, along the cover from the oscillator region to other components in the tuner, and in particular to the input or output connectors.

Abstract: A method of programming a memory cell (100), the method comprising applying a first electric potential to a first electric terminal (101) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity to thereby generate second charge carriers of a second type of conductivity by impact ionisation of the accelerated first charge carriers, and applying a second electric potential to a second electric terminal (102) of the memory cell (100) to accelerate the second charge carriers to thereby inject the second charge carriers in a charge trapping structure (103) of the memory cell (100).

Abstract: An integrated circuit comprises a device under test and embedded test circuitry. The embedded test circuitry comprises a plurality of process monitoring sensors (14), a threshold circuit (22) for comparing the sensor signals with a threshold window having an upper and a lower limit and a digital interface (17) for outputting the threshold circuit signal. The process monitoring sensors (14) comprise circuitry based on the circuit elements of the device under test. This arrangement enables monitoring of circuit element performance, such as transistor properties, using process monitoring sensors which are embedded with the device under test, so that the same process parameter variations apply to the sensors as to the device under test. The sensors preferably match the physical layout of the device under test.

Abstract: The present invention relates to a polar transmission method and a polar transmitter for transmitting phase and amplitude components derived from in-phase (I) and quadrature-phase (Q) components of an input signal. A first conversion is provided for converting the in-phase (I) and quadrature-phase (Q) components into the phase and amplitude components at a first sampling rate. Additionally, a second conversion is provided for converting the phase component into a frequency component, wherein the second conversion comprises a rate conversion for converting the first sampling rate into a lower second sampling rate at which the frequency component is provided. Thereby, the second sampling rate can be used as a lower update rate in a digitally controlled oscillator in order to save power or because of speed limitations, while the surplus phase samples obtain due to the higher first sampling rate enable better approximation of the phase component after the digitally controlled oscillator.

Abstract: The present invention relates to electromigration testing and evaluation methods and apparatus for a device under test with an interconnect structure. The method comprises forcing the occurrence of a step resistance-increase of the interconnect structure due to electromigration in the first layer and subsequently subjecting the interconnect structure to at least three respective predetermined stress conditions while concurrently measuring a test quantity indicative of an electrical resistance of the interconnect structure. The method allows performing an electromigration test in much shorter time than known electromigration testing methods, without loss of information or accuracy. It is therefore possible to accelerate the optimization of the interconnect manufacturing process so that the conductor electromigration kinetics remains compatible with a required product lifetime.

Abstract: An integrated circuit (100) is disclosed that comprises a plurality of data processing stages (110) and a data communication network comprising a plurality of data communication paths between the data processing stages (110). Each data processing stage (110) comprises a hardware layer (160) for processing data received through a data communication path and a software layer (120) arranged to communicate with the software layers of selected other data processing stages for controlling the synchronization of the data communication between the data processing stage (110) and the selected other data processing stages in response to dynamically assigned communication relationships between data processing stage (110) and the respective selected other data processing stages.

Abstract: The present disclosure provides a method for controlled formation of the resistive switching layer in a resistive switching device. The method comprises providing a substrate (2) comprising the bottom electrode (10), providing on the substrate a dielectric layer (4) comprising a recess (7) containing the metal for forming the resistive layer (11), providing on the substrate a dielectric layer (5) comprising an opening (8) exposing the metal of the recess, and forming the resistive layer in the recess and in the opening.

Abstract: A photosensitive device (100), the photosensitive device (100) comprising a substrate (101) and a plurality of vertically aligned nanowire diodes (102 to 105) provided on and/or in the substrate (101).

Abstract: A novel high-speed differential receiver is disclosed that provides a new method and apparatus receiving and amplifying a small differential voltage with a rail-to-rail common mode voltage. The receiver output signals are differential signals with low skew and high symmetry. This high-speed differential receiver is based on a common mode voltage normalization, which is based on a differential phase splitting methodology, before the resulting signal is recombined, normalized and amplified. The method involves using a differential signal splitting followed by a common mode voltage normalization stage, then a controlled gain transimpedance amplification, and then amplification using one or two rail to rail amplification stages that are symmetrical and balanced in nature.

Abstract: A processing element (1) forming part of a parallel processing array such as SIMD comprises an arithmetic logic unit (ALU) (3), a multiplexer (MUX) (5), an accumulator (ACCU) (7) and a flag register (FLAG) (9). The ALU is configured to operate on a common instruction received by all processing elements in the processing array. The processing element (1) further comprises a storage element (SE) (11), which supports the processing of local customized (i.e. data dependent) processing in the processing element (1), such as lookup table operations and the storing local coefficient data.

Abstract: The invention relates to a method, in a transmission system providing a set of multiplexed services transported on specific transport channels forming a single composite transport channel and having predetermined quality factors corresponding to required error rates which necessitate adequately adjusted individual transmission powers, for balancing the current individual transmission powers of said multiplexed services during a communication in order to satisfy the multiplexed service quality requirements while limiting the interference level. The method comprises a step of determining rate-matching coefficients enabling to balance the individual transmission powers of the multiplexed services with respect to the global transmission power on the composite transport channel, a step of transmitting, using said determined rate-matching coefficients and a step of adapting said rate-matching coefficients with respect to measured error rates of the multiplexed services on the specific transport channels.

Abstract: The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises a first latch circuit for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch circuit for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch circuit for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Furthermore, the charge pump circuit comprises a differential input circuit and a control circuit for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement.

Abstract: A power supply module arrangement with an integrated circuit mounted on a bearing unit and a power supply includes an integrated circuit mounted on a bearing unit and a power supply module arrangement that is placed on the combination of bearing unit and integrated circuit. The power supply module arrangement includes a base extending at least partially over the base of the integrated circuit and/or all around the base of the integrated circuit. The power supply module arrangement allows for greater permissible load jumps, greater permissible current change rates and ever tighter tolerances regarding the constancy of the supply voltage.

Abstract: A circuit for producing multiple switching control signals for a harmonic rejection mixer from multiple phases of a digital local oscillator signal is presented, wherein a first waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one switching control signal by logical combining two from the multiple phases of a digital local oscillator signal, and a second waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one first switching control signal by logical combining one from the multiple phases of a digital local oscillator signal with a predetermined signal having a static logical value.

Abstract: A system and method for synchronizing otherwise independent oscillators private to I2C Bus slave devices. An I2C Bus master device can issue two new general call commands, CALIBRATE and ZERO COUNTERS. The I2C Bus slave devices respond to the CALIBRATE command by counting the number of cycles its local, private oscillator makes through during the communication transfer period of the CALIBRATE command on the I2C Bus. All such I2C Bus slave devices measure the same communication transfer period on the I2C Bus, so the differences in the digital measurements obtained by each of them are proportional to their respective oscillator frequencies. The digital measurements are privately used by each I2C Bus slave device to calculate appropriate oscillator prescale factors, and to automatically load the values that will harmonize the final product frequencies of all of the local oscillators on all of the I2C Bus slave devices in the system.