Abstract: A method of manufacturing a transistor (300), the method comprising forming a gate (101) on a substrate (102), forming a spacer (201) on lateral side walls of the gate (101) and on an adjacent portion (202) of the substrate (102), modifying material of the spacer (201) so that the modified spacer (301) covers only a lower portion (303) of the lateral side walls of the gate (101), and providing source/drain regions (301) in the modified spacer (301).

Abstract: The present application relates to an apparatus comprising a first transistor element, with at least three terminals, and at least one switching unit. The present application relates also to a method, computer readable medium having a computer program stored thereon and a track and hold circuit comprising the apparatus. The apparatus comprises a first transistor element with at least three terminals, wherein a first terminal is supplied with a first voltage, and wherein a second terminal is supplied with a second voltage. The apparatus comprises a first switching unit, wherein a third terminal is connected to ground potential via the first switching unit. The transistor element comprises a predefined threshold voltage. The first voltage and the second voltage are predefined alternating voltages.

Abstract: A method is provided of manufacturing a semiconductor device comprising a first, n-type field effect transistor (1) and a second, p-type field effect transistor (2). The method comprises depositing a gate dielectric layer over a substrate; depositing a gate metal layer (22) over the gate dielectric layer, depositing a solid metal oxide layer (15) over the gate dielectric layer; removing a portion of the solid metal oxide layer (15) over an area of the substrate corresponding to the n-type transistor; and completing gate stacks for the n-type and p-type transistors and forming source and drain regions. The invention thus provides a device which is compatible with IC technology and easy to manufacture. The deposition of a solid metal oxide layer provides a simplified manufacturing process, by avoiding the complexity of gas exposure to form an oxide layer.

Abstract: An electronic device (100), the electronic device (100) comprising a substrate (101), a convertible structure (102) arranged on and/or in the substrate (101), being convertible between at least two states by heating and having different electrical properties in different ones of the at least two states, wherein the convertible structure (102) has a first portion having a first width (w1), and has a second portion having a second width (w2), the second width (w2) being smaller than the first width (w1), and a protrusion (108) protruding through the convertible structure (102) to thereby narrow the second portion of the convertible structure (102) from the first width (w1) to the second width (w2).

Abstract: An analog to digital conversion circuit comprises a first digital noise cancellation filter (16) configured to provide a signal to cancel quantization noise from an analog to digital converted output signal. In a calibration phase a second digital noise cancellation filter (26) is has an input coupled to an input of the first digital noise cancellation filter (16). Mutually different sets of least one-filter coefficients are programmed in the first and second digital noise canceling filters (16, 26). A difference is computed of averaged size indications of digital output signals derived using signals from the first and second digital noise cancellation filters (16, 26) using the same input signal. Updates of the sets of at least one filter coefficients are adapted dependent on the difference between the averaged size indications.

Abstract: The invention relates to a slave bus subscriber for a serial data bus with a master bus subscriber, wherein the slave subscriber recognizes the bit rate of a data packet received over the data bus, whose header has a sync break field, a sync field and an ID field, with the help of the header of the data packet in such a manner that the periods between falling edges of bits having known bit intervals at least of the sync field and of the sync break field are evaluated and the bit rate is determined from the evaluated periods.

Abstract: A device (100) for managing a plurality of software items, the device (100) comprising an analysis unit (103) adapted for analyzing a functional correlation between the plurality of software items, and a grouping unit (105) adapted for grouping functionally correlated ones of the plurality of software items together in a common memory space.

Abstract: A digital signal processing circuit comprises a band selector (14) for selecting at least one sub-band from a frequency spectrum of a digital sampled input signal. The band selector (14) comprises a plurality of processing branches corresponding to respective phases and an adder (28a, 28b) for adding branch signals from the branches. Each branch comprises a subsampler (20a,b) for sub-sampling sample values of the input signal at the phase corresponding to the branch, a filter (24a,b) with a first FIR filter (32, 34), applied alternatingly to sets of even and to sets of odd samples from the subsampler (20a,b) and a second FIR filter (36, 38) applied to further sets of odd and even samples from the subsampler (20a,b) when the first FIR filter is applied to the even and odd sets respectively.

Abstract: The invention relates to a circuit and method for receiving a signal of which—at the receiver end—the frequency is basically unknown. By sampling the data and deriving the frequency of the signal (or actually: the data rate of the data carried by the signal) and setting a phase locked loop in the receiver to the derived—estimated—circuit, the receiver can very quickly tune in to the frequency of the signal. Hence, no embedded or accompanying clock is required for the signal. Oversampling of the signal by the receiver front end is preferred, though.

Abstract: A method for generating a public key for an electronic device is provided, wherein the method comprises generating a public key 103 based on a private key and a unique identifier associated with the electronic device 200.

Abstract: The novelty of the invention consists in that it makes possible to improve the known device having the same purpose (UA Nr 78002) by the novel design of the transmitter and receiver antennas and the circuits for connecting them to an electric power generator and a load resistor. The invention discloses the experiment for transmitting power of 10 W at a distance of 1.8 m with an output ratio of ?1 which proves the industrial applicability of the invention.

Abstract: A method of transferring content (CONT1, CONT2) between at least two devices (DEV1, DEV2, DEV3), the devices (DEV1, DEV2, DEV3) being capable of outputting said content (CONT1, CONT2), and a device (DEV1) itself is disclosed. First, said devices (DEV1, DEV2, DEV3) are connected via associated interfaces (INT1, INT2, INT3). Then, there is a detection or negotiation which of the devices (DEV1, DEV2, DEV3) is currently outputting content (CONT1, CONT2). Finally, content (CONT1, CONT2), which is currently being output, is transferred from the corresponding outputting device or devices (DEV1, DEV2) to the other device or devices (DEV1, DEV2, DEV3) via said interfaces (INT1, INT2, INT3).

Abstract: The invention relates to a method and a system for synchronizing a debugging process of a multiprocessor system (1) with a number of processors (2.1 to 2.3), comprising the following steps: —if for one of the processors (2.1 to 2.3) a debugging process is requested by a STOP-signal (STOP#2.1 to STOP#2.3) a HALT-signal (HALT#2.1 to HALT#2.3) to the other processors (2.1 to 2.3) is asserted until their STOP-signal (STOP#2.1 to STOP#2.3) for debugging request is asserted to them, —asserting a respective HALT-signal (HALT#2.1 to HALT#2.3) to each processor (2.1 to 2.3) which has finished the debugging process until the other processors (2.1 to 2.3) have finished their respective debugging processeS, —starting all processors (2.1 to 2.3) synchronously after all HALT-signals (HALT#2.1 to HALT#2.3) and/or STOP-signals (STOP#2.1 to STOP#2.3) are de-asserted and all debugging processes are finished.

Abstract: Various aspects of the present invention are directed to design modeling and/or processing of streaming data. According to an example embodiment, a system to model a hardware specification includes a platform (106) arranged to receive an input data stream and transmit an output data stream. The system also includes a source (102) for a streaming application adapted to provide the input data stream at a source data rate, a destination (104) for the streaming application adapted to consume the output data stream at a destination data rate, and a data channel (110) coupling the platform and a computer (108). The computer uses the hardware specification to generate intermediate data streams, which, in turn, are used to streamline the modeling for the platform.

Abstract: The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1). Because of that, the erase gates (10) do not add to the cell size. The capacitance between the erase gate (10) and the floating gate (16) is small compared with the capacitance between the control gate (19) and the floating gate (16), and the charged floating gate (16) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate (10) and the floating gate (16).

Abstract: An antenna assembly for wireless communication equipment comprises an antenna structure comprising at least a loop type antenna arranged to deliver a first current when it is used in a balanced mode and/or a second current when it is used in an unbalanced mode with respect to a ground plane from received radio signals, and current extraction device coupled to the antenna structure and arranged to be placed in at least a first state in which the current extraction device delivers the first or second current and a second state in which the current extraction device simultaneously delivers the first and second currents either separately or mixed together.

Abstract: A circuit arrangement for supporting and monitoring a microcontroller, which is constructed externally of the microcontroller, comprises a watchdog circuit for monitoring the microcontroller, which circuit outputs an error signal if not reset by the microcontroller within a watchdog period, and an interrupt circuit, which feeds important system messages to the microcontroller as interrupt events for processing. In order correctly to combine interrupt processing and watchdog operation, the watchdog circuit is connected to the interrupt circuit and cooperates therewith in such a way that the interrupt circuit feeds at most a predetermined number of interrupt events to the microcontroller within a watchdog period.

Abstract: An oscillator circuit has a first and a second piezoresistive resonator (1,2), each having a resonant frequency, each piezoresistive resonator having an input for driving the resonator, and each piezoresistive resonator having its input coupled directly to an output of the other of the resonators, to provide feedback according to a resistance of the respective resonator without amplification and without a phase shifter. This enables feedback without the need for another component to provide the phase shift. This means a simpler circuit can be used, which can facilitate greater integration and hence lower costs. By using piezoresistive resonators the need for an external crystal can be avoided, enabling greater integration and lower costs.

Abstract: An electronic apparatus with a USB connection has a functional circuit with a processor, a parallel address data bus couple to the processor and a USB device controller circuit with a USB interface in parallel with said address/data bus. The apparatus contains an interface integrated circuit electronically between the USB connection on one hand and the parallel address/data interface and the USB interface on the other hand. The interface integrated circuit has external terminals for connecting to a USB bus, a transceiver capable of transceiving for both a USB host and a USB device, the transceiver having a USB interface, a host interface and a device interface. The USB interface is coupled to the USB connection. The device interface is connected to the external USB device controller circuit. A host controller is coupled to the host interface, the host controller being coupled to the functional circuits via the parallel data/address bus.

Abstract: An electronic device (ICD) comprises an integrated circuit (AIC) and a capacitance element (PIC). The integrated circuit (AIC) is provided with a plurality of circuit contact pairs (CI). The capacitance element (PIC) is provided with a plurality of capacitance contact pairs (CC). A capacitance is present between each of at least part of the capacitance contact pairs (CC). The plurality of capacitance contact pairs (CC) faces the plurality of circuit contact pairs (CI). At least a part of the capacitance contact pairs (CC) is electrically coupled in a pair-by-pair manner to at least a part of the circuit contact pairs (CI).