Abstract: A video display system (100) is provided which comprises a display panel (DP) for displaying a video signal (V), at least one lighting unit (LU) for providing a surround or ambient lighting (LS), a user interface (UI) for receiving external user calibration signals and a lighting control unit (LC) for controlling the color and/or luminance of the lighting unit (LU) in dependence on the calibration signals received by the user interface (UI).

Abstract: In photo-lithography, one may assess the effect of flare due to various exposure tools. In an example embodiment, in a photo-lithography process on a photo resist coated substrate, there is a method for determining the effect of flare on line shortening. The method comprises, at a first die position on the substrate and in a first exposure, printing a first mask that includes a flare pattern corresponding to one corner of the first mask, and in a second exposure, printing a second mask that includes another flare pattern corresponding to an opposite corner of the second mask. At a second die position on the substrate, a composite mask pattern based on features of the first mask and the second is printed. The printed patterns are developed and measurements are obtained therefrom. The effect of flare is determined as a function of the measurements.

Abstract: The invention relates to an electronic device that includes an MCML Muller-c element. The MCML Muller-c element has a first differential stage for operating in a trans-conductance state converting the differential input to a differential output current implementing the logical behavior of the MCML Muller-c element and a second stage operating as a trans-impedance stage being coupled to the first stage. Further, the MCML Muller-c element has peaking circuitry being coupled to the first stage, such that the peaking circuitry and the first stage provide a negative capacitance to the MCML Muller-c element for reducing the damping factor of the MCML Muller-c element.

Abstract: A method of setting the slice level (SL) in a binary signal (T) comprises measuring the noise level at both signal levels (A,B) and adjusting (Z) the slice levels in dependence upon the measured noise levels. By weighing the noise levels, asymmetric noise is taken into account. A device (10) for setting the slice level comprises level shift means and noise peak level detection means.

Abstract: The method of manufacturing an integrated circuit (IC) according to the invention starts with providing a pre-fabricated integrated circuit (10) comprising an electrical device (2) and having a surface (11) coated with a dielectric material (12) and a metal (15). The dielectric material (12), which may be separated from the metal (15) by the barrier layer (14), has an opening (13), which is filled with the metal (15). Portions of the metal (15) outside the opening (13) are removed by polishing for a first period of time, after which an etching agent (25) is added to the polishing liquid (24) and polishing is continued for a second period of time for removing portions of the metal (15) remaining outside the opening (13). The polishing apparatus (40) is able to perform the method.

Abstract: A metal-base transistor is suggested. The transistor comprises a first and a second electrode (2, 6) and base electrode (6) to control current flow between the first and second electrode. The first electrode (2) is made from a semiconduction material. The base electrode (3) is a metal layer deposited on top of the semiconducting material forming the first electrode. According the invention the second electrode is formed by a semiconducting nanowire (6) being in electrical contact with the base electrode (3).

Abstract: The present invention relates an RF tuner module that comprises one or more standard RF connectors. As, relative big, standard RF connectors are widely in use but at the same time there is a pressure to make products smaller an RF tuner module design is size constrained. The invention describes a measure to make an RF tuner module, with a standard RF-connector, smaller by extending one of the shielding sides of the RF tuner in order to facilitate a proper mounting of the RF connector to the RF tuner module.

Abstract: Data, stored in MRAM-cells (12) should be protected against misuse or read-out by unauthorised persons. The present invention provides an array (10) of MRAM-cells (12) provided with a security device (14) for destroying data stored in the MRAM-cells (12) when they are tampered with. This is achieved by placing a permanent magnet (16) adjacent the MRAM-array (10) in combination with a soft-magnetic flux-closing layer (18). As long as the soft-magnetic layer (18) is present, the magnetic field lines (20) from the permanent magnet (16) are deviated and flow through this soft-magnetic layer (18). When somebody is tampering with the MRAM-array (10), e.g. by means of reverse engineering, and the flux-closing layer (18) is removed, the flux is no longer deviated and affects the nearby MRAM-array (10), thus destroying the data stored in the MRAM-cells (12).

Abstract: The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1). Because of that, the erase gates (10) do not add to the cell size. The capacitance between the erase gate (10) and the floating gate (16) is small compared with the capacitance between the control gate (19) and the floating gate (16), and the charged floating gate (16) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate (10) and the floating gate (16).

Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programming of parallel slave devices concurrently using an I2C serial bus. At least two slave devices are coupled in parallel on the data transfer bus and configured to load serial data over the serial data line using the communications protocol. Each slave device includes a programmable configuration register configured to be programmed, using the communications protocol, to select one of a plurality of selectable slave device configurations. One of the selectable slave device configurations causes the at least two slave devices to load the serial data in parallel, and another of the selectable slave device configurations causes the at least two slave devices to be loaded one at a time.

Abstract: An integrated circuit (1) comprises a monitor (M1, M3, M3) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit (1); and a self test controller (28) connected to receive monitor data from the monitor (M1, M2, M3). The self-test controller is also operable to output self test data from the integrated circuit. The monitor includes an output shift register (SR1, SR2, SR3) and is operable to output monitor data through the shift register (SR1, SR2, SR3). Such a system enables simplified communication of system self test results on an integrated circuit.

Abstract: In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern (305) in a wafer-level chip-scale (WLCS) package (300). The method includes depositing a metal layer (5, 10, 15) on a first dielectric layer (315) and filling (20) in bond pad openings (310) and bump pad openings (330); the metal layer (360) has atop (340) and bottom (360) layer. In the metal layer (360), bond pad connections (310) and bump pad connections (330) are defined (25, 30) by removing the top layer of metal in areas other than at bond pad openings (310) and bump pad openings (330), and leaving the bottom layer (360) of metal in areas without bond pad or bump pad connections. In the bottom metal layer, connection traces between the bond pad and bump pad are defined (35, 40). A second organic dielectric layer (325) is deposited (45) on the silicon substrate (305), enveloping the circuit pattern.

Abstract: The system and method of the present invention provide a single mixer (200-400) with significantly reduced noise performance at a low cost by adding a current control circuit (109) that reduces the current in at least the switching stage (103, 303, 403) during polarity changes of the local oscillator (LO) signal (104). Alternative embodiments (300-400) are provided for a single mixer having significantly reduced noise wherein the low-noise characteristic is enhanced by a further modification to the switching stage (303-403).

Abstract: A method for determining a relative position of a first camera with respect to a second camera, comprises the followings steps: Determining at least a first, a second and a third position of respective reference points with respect to the first camera, Determining at least a first, a second and a third distance of said respective reference points with respect to the second camera, Calculating the relative position of the second camera with respect to the first camera using at least the first to the third positions and the first to the third distances.

Abstract: A method of forming a field effect transistor comprising a gate formed on an insulating layer, the gate having, in a zone in contact with the insulating layer, a semiconducting central zone and lateral zones in the length of the gate, the method comprising forming a gate comprising a portion of insulating layer, a portion of semiconducting layer formed over the insulating layer, and a portion of mask layer formed over the semiconducting layer; performing an etching of the portion of the mask layer such that only a portion in the centre of the gate remains; and reacting the semiconducting gate with a metal deposited over the gate.

Abstract: A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from the output signal from the respective one of the memory cells (10). A reference generator circuit (24, 26) forms the reference signal from a sum wherein each respective one of the memory cells (10) of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (10). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal.

Abstract: A device (100) for processing image data representative of an object (201), wherein the device (100) comprises a first image-processing-unit (101) adapted for generating three-dimensional image data (102) of the object (201) based on two-dimensional image input data (103 to 105) representative for a plurality of two-dimensional images of the object (201) from different viewpoints, a second image-processing-unit (106) adapted for generating two-dimensional image output data (107) of the object (201) representative of a two-dimensional view of the object (201) from a predefined viewpoint, and a transmitter unit (109) adapted for providing the two-dimensional image output data (107) for transmission to a communication partner which is communicatively connectable to the device (100).

Abstract: A method for transmitting data is described that includes the steps of: Producing a data frame for transmission, the data frame including a sequence number and user data, saving a copy of the data frame in a retransmission buffer, and if said step of saving a copy requires that data already present in the retransmission buffer is overwritten, selecting the one or more oldest data frames in the retransmission buffer to be overwritten, in case an error is determined in the received data frame, communicating an error message to the transmitter of the data frame, which error message at least comprises an indication of the sequence number of the last correctly received data frame—upon receipt of such message and if available, retransmitting one or more data frames from the retransmission buffer having a sequence number higher than the sequence number communicated in the message.

Abstract: A method of forming an interconnect structure in a semiconductor device in which via holes (62) defined in a dielectric layer are filled with a filler material (64), such as a porogen material, before a further dielectric layer (66) is deposited thereover. Trenches (72) are formed in the further dielectric layer and then the filler material exposed thereby in the via holes is removed. The method provides a robust process which affords improved via and trench profile control.

Abstract: A method and apparatus for efficiently generating complex sinusoids of a desired frequency by multiplying a phasor by a predetermined value once every sampling interval, and using the highest order bits within the phasor to identify if the phasor is at an integer multiple 45 degrees and substituting components in the phasor if it is determined that the phasor is an integer multiple of 45 degrees. If the phasor is not identified as being an integer multiple of 45 degrees then an error factor for both the real and imaginary components is determined and the real and imaginary components are corrected by removing the error factor.