Abstract: A multi-phase frequency divider comprises dynamic inverters connected in a ring and the intermediate nodes around the ring are stabilized with cross-coupled latches. Clock input pulses enable each dynamic inverter's output and will force a corresponding change-of-state in the cross-coupled latches. The multi-phase output is presented in parallel on all the latches.

Abstract: The electromechanical transducer (1) has a resonator element (20) and an actuator (30) for inducing an elastic deformation of the resonator element (20) dependent on the electrical input signal. For temperature stabilization, the electromechanical transducer (1) has a sensing element (40) for providing an electrical sensing signal has a function of a temperature of the resonator element (20), and a heating element (50) for heating the resonator element to reduce the temperature dependent frequency deviation to keep the resonance frequency equal to the nominal frequency at operating temperature. The heating element (50) is controlled by an electrical heating signal based on the electrical sensing signal. The resonator element may have the hating element or the sensing element; it may be part of a wheatstone bridge; it may consist of two longitudinally extendable parts (201, 202) extending in opposite directions, being attached in a support area (204) in a deformation free part (203).

Abstract: A read only memory matrix in an integrated circuit contains data transistors coupled to both the bit lines and the word lines in data dependent ones of the cells of the matrix. A differential sense amplifier has a first input coupled to a bit line, a second input coupled to a reference circuit and a control input for controlling activation and deactivation of amplification by the sense amplifier. A coupling circuit controllably permits charge sharing between a selectable one of the bit lines and the first input. A timing circuit is arranged to signal operation in a first phase, when the word lines have selected a row of the matrix, followed by a second phase. The timing circuit controls the coupling circuit to permit charge sharing between the input and the selectable one of the bit lines in the first phase.

Abstract: The semiconductor device of the invention includes a circuit and a protecting structure. It is provided with a first and a second security element and with an input and an output. The security elements have a first and a second impedance, respectively, which impedances differ. The device is further provided with a measuring unit a processing unit and a connection unit. The processing unit transform any first information received into a specific program of measurement. Herewith a challenge-response mechanism is implemented in the device.

Abstract: The present invention relates to a receiver apparatus, analog-to-digital converter apparatus, and method of converting an analog input signal into a digital output signal, wherein an additional direct feedforward path is introduced to compensate for peaking of feedforward structures while preserving frequency selectivity of the feedforward topology. In particular, the direct feedforward path (72) is provided with a scaling by a direct feedforward coefficient (ao) greater than zero and less than one. As a result, overshoot or peaking of classical feedforward topologies can be suppressed while providing interferer immunity, anti-aliazing effects and loop stability.

Abstract: An efficient implementation of zero knowledge protocols for authentication of devices and for identification of devices connecting to a network. According to one aspect, the present invention provides a method of verifying the knowledge of a secret number s in a prover device by a verifier device having no knowledge of the secret number, with a zero-knowledge protocol using the Montgomery representation of numbers and Montgomery multiplication operations therein.

Abstract: The invention relates to a method of manufacturing a semiconductor strained layer and to a method of manufacturing a semiconductor device (10) in which a semiconductor body (11) of silicon is provided, at a surface thereof, with a first semiconductor layer (1) having a lattice of a mixed crystal of silicon and germanium and a thickness such that the lattice is substantially relaxed, and on top of the first semiconductor layer (1) a second semiconductor layer (2) is provided comprising strained silicon, in which layer (2) a part of the semiconductor device (10) is formed, and wherein measures are taken to avoid reduction of the effective thickness of the strained silicon layer (2) during subsequent processing needed to form the semiconductor device (10), said measures comprising the use of a third layer (3) having a lattice of a mixed crystal of silicon and germanium.

Abstract: A quadrature transmitter and receiver have configurable I and Q channel paths that facilitate the application of selected test signals to determine gain and phase imbalances introduced by the transmitter and receiver. In a first ‘normal’ configuration, the I and Q channels are independently tested by applying an I-only test signal, followed by a Q-only test signal. In a second ‘switched transmitter’ configuration, the Q-only test signal is again applied. In a third ‘switched receiver’ configuration, the I-only test signal is again applied. By combining the results, gain and phase imbalances of the transmitter and the receiver can be determined. In a preferred embodiment, these configurations and test signals are applied within a single transceiver that has the output of its transmitter closed-loop coupled to the input of its receiver.

Abstract: The invention relates to an electronic device for cryptographic processing, having at least two electronic circuits (IC, CC, CP) coupled via a connection means, wherein the connection means is arranged for transferring data signals between the two electronic circuits. The electronic device further has a monitoring circuit (401) arranged to monitor a deviation in the capacitance of the connection means. In case the deviation exceeds a predetermined value an alert signal (411) is generated.

Abstract: A method of manufacturing a semiconductor device such as a MOS transistor. The device comprises a polysilicon gate (10) and doped regions (22,24) formed in a semiconductor substrate (12), separated by a channel region (26). The exposed surface of the semiconductor substrate is amorphized, by ion bombardment for example, so as to inhibit subsequent diffusion of the dopant ions during thermal annealing. Low thermal budgets are favoured for the activation and polysilicon regrowth to ensure an abrupt doping profile for the source/drain regions. As a consequence an upper portion (10b) of the gate electrode remains amorphous. The upper portion of the gate electrode is removed so as to allow a low resistance contact to be made with the polysilicon lower portion (10a).

Abstract: A planar antenna device (AD) for a TV receiver (R) comprises i) a loop antenna (LA) comprising first (E1) and second (E2) ends spaced one from the other, ii) a tuning means (TM) connected to the first (E1) and second (E2) ends of the loop antenna (LA) and arranged to control the frequency of the VHF TV signals this loop antenna (LA) is able to receive from command signals, iii) a first ground plane (GP1) cooperating with the loop antenna (LA) in order to act as a UHF monopole in receiving TV signals with UHF frequencies, iv) a first coupling means (CM1) coupled to the loop antenna (LA) at a first chosen location and arranged to deliver the received VHF signals, v) a second coupling means (CM2) coupled to the loop antenna (LA) at a second chosen location and arranged to deliver the received UHF signals, vi) an amplification means (AM) coupled to the first ground plane (GP1) and arranged to amplify TV signals, and vii) a switching means (SM) arranged to couple the amplification means (AM) to the first coupling

Abstract: The present invention relates to a method for manufacturing an electronic assembly (50) comprising an electronic component, a cavity and a substrate which method comprises; —providing an electronic component (10) having a first pattern with a substantially closed configuration; —providing a cover (18) on a surface of the electronic component, which cover together with said surface defines a cavity (20), the closed configuration of the first pattern substantially enclosing the cover at said surface; —providing a substrate (30) having a second pattern with a substantially closed configuration, which closed configuration at least partially corresponds to the closed configuration of the first pattern and comprises a solder pad; —disposing solder material at the solder pad; —positioning the electronic component and the substrate so as to align both the substantially closed configurations of the first and second pattern, while the substrate supports a top surface (28) of the cover; —reflow-soldering the solder mate

Abstract: The present invention relates to a method for controlling a sleep mode of a device in a wireless communications network or in a mobile point-to-point connection in order to turn off system components of the device, especially to turn off a medium access control (2) comprising the steps of: receiving a sleep mode information from an application module in a medium access control (2), coupled to an extended physical layer (PHY), especially to a base band (3), transferring the sleep mode information from the medium access control (2) to the base band (3), setting a sleep signal (sleep) of a power management mode (PMMode) to set one of the system components into sleep state, and, additionally, starting a predetermined first delay timer (T1) to delay the setting of the sleep state for one of the system components.

Abstract: It is described a method for providing an electronic key within an integrated circuit (100) including both a volatile memory (102) and a non-volatile memory (104). The described comprises starting up the integrated circuit (100), reading the logical state of predetermined data storage cells (102a) assigned to the volatile memory (102), which data storage cells (102a) are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and generating an electronic key by using the logical state of the predetermined data storage cells (102a). Preferably, the predetermined data storage cells (102a) are randomly distributed within the volatile memory (102). It is further described an integrated circuit (100) for providing an electronic key.

Abstract: The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with an connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. It is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) comprising a field effect transistor, in which method a semiconductor body of silicon (12) with a substrate (11) is provided at a surface thereof with a source region (1) and a drain region (2) of a first conductivity type which are situated above a buried isolation region (3,4) and with a channel region (5), between the source and drain regions (1,2), of a second conductivity type, opposite to the first conductivity type, and with a gate region (6) separated from the surface of the semiconductor body (12) by a gate dielectric (7) and situated above the channel region (5), and wherein a mesa (M) is formed in the semiconductor body (12) in which the channel region (5) is formed and wherein the source and drain regions (1,2) are formed on both sides of the mesa (M) in a semiconductor region (8) that is formed using epitaxial growth, the source and drain regions (1,2) thereby contacting the channel region (5).

Abstract: The present invention relates to a 4-level logic decoder for decoding n 4-level input data signals into n 2-bit signals. The 4-level logic decoder comprises n decoding circuits with each decoding circuit comprising comparison circuitries for comparing the 4-level input data signal with a clock signal and a one-bit data signal. In dependence upon the comparison results signals are provided to a decode logic circuit, which are indicative of a data bit value of the 4-level input data signal representing one of the clock signal, the one-bit data signal, and static values of the 4-level input data signal. In dependence upon the signals the decode logic circuit generates then a 2-bit output data signal. The 4-level logic decoder is easily implemented using simple circuit of logic components, which allow modeling using an HDL.

Abstract: In an example embodiment, there is a test module for testing the susceptibility of an integrated circuit design to latch-up. The test module comprises a plurality of test blocks, connected in parallel. Each test block includes an injector block for applying a stress current of voltage to the respective test block and a plurality of sensor blocks located at successively increasing distances from the respective injector block. Each sensor block includes a PNPN latch-up test structure. The present invention combines the respective advantages of IC stress current testing and latch-up parameter measurement using a standard PNPN latch-up test structure.

Abstract: The invention concerns an arrangement on a semiconductor chip for calibrating temperature setting curve having a signal generation unit (2) for providing a first signal (Iptat1, Vptat1, fptat1), which is proportional to the actual uncalibrated temperature T1 of the chip. To avoid bringing the chip on a second temperature it is proposed to read a first signal (Iptat1, Vptat1, fptat1), which is proportional to the actual uncalibrated temperature T1 of the chip and generate a signal offset (Ivirt, Vvirt, fvirt), which is combined with the first signal (Iptat1, Vptat1, fptat1) defining a second signal (Iptat2, Vptat2, fptat2) and to extract a first actual temperature T1 from the first signal (Iptat1, Vptat1, fptat1) and a second uncalibrated temperature T2 from the second signal (Iptat2, Vptat2, fptat2).

Abstract: An integrated tuner comprises a step AGC amplifier (1) that is adjusted only during a vertical synchronization interval. A receiver comprises such an integrated tuner and an IF demodulation circuit (5,6) for providing a vertical sync signal to the integrated tuner.