Abstract: The invention concerns an arrangement on a semiconductor chip for calibrating temperature setting curve having a signal generation unit (2) for providing a first signal (Iptat1, Vptat1, fptat1), which is proportional to the actual uncalibrated temperature T1 of the chip. To avoid bringing the chip on a second temperature it is proposed to read a first signal (Iptat1, Vptat1, fptat1), which is proportional to the actual uncalibrated temperature T1 of the chip and generate a signal offset (Ivirt, Vvirt, fvirt), which is combined with the first signal (Iptat1, Vptat1, fptat1) defining a second signal (Iptat2, Vptat2, fptat2) and to extract a first actual temperature T1 from the first signal (Iptat1, Vptat1, fptat1) and a second uncalibrated temperature T2 from the second signal (Iptat2, Vptat2, fptat2).

Abstract: A receiver for a multi-carrier communication system has a channel corrector (173) which receives an input signal (CDC2) and a correction control signal (EC) to correct an amplitude and/or phase of the input signal (CDC2) to obtain a corrected signal (ED). A channel estimator (19) has a slicer (190) which performs a hard-decision on the corrected signal (ED) to obtain a decided signal (HDS). The correction control signal (EC) is dependent on a difference between the input signal (CDC2) and the decided signal (HDS) to decrease said difference.

Abstract: A method and system for synchronizing signals. First and second signals are sent (compressed or uncompressed) from a source to a receiving apparatus of a receiving system. The first signal has content of a first modality (e.g., audio) and the second signal has content of a second modality (e.g., video). The first and second signals are to be displayed on a display apparatus of the receiving system. The first and second signals have been time-synchronized at the source. If the first and second signals are not synchronized in time when received at the receiving apparatus, then the first and second signals may be time-synchronized at the receiving apparatus either manually or through timestamping of both signals at the source, in conjunction with use of a real-time clock at the receiving apparatus.

Abstract: This description is given of a use-authorization device for security-related applications, in particular access control to secure areas or securing vehicles with a user operated key unit for generating consecutive, alternating user code information which exhibits a sequence of consecutive function values vi+1=F(vi, const) for i=0, . . .

Abstract: A generic apparatus (14) re-orders video data for various types of displays, such as plasma discharge panels (PDPs), digital micro-mirror devices (DMDs), liquid crystal on silicon (LCOS) devices, and transpose scan cathode ray tube (CRT) displays. In one embodiment, the apparatus (14) includes a first programmable transpose processor (18), a memory (20, 120), and a second programmable transpose processor (22, 122) fabricated as a single IC unit.

Abstract: In a method for determining the bearing surface in images of skin prints, the skin having ridges and furrows and the images existing in the form of image data, the image is filtered with a plurality of Gabor filters whose cosine functions are oriented in different directions in the spatial domain. From the filter responses, surfaces are determined that are each distinguished by an approximate direction of the ridges/furrows, which direction is preset by the respective Gabor filter. The surfaces are combined to an overall surface that represents the bearing surface.

Abstract: The invention relates to a secure data processing system including an unscrambling module [DSC] disposed on a dedicated hardware part [HW] of an integrated circuit and intended to unscramble a stream of data [SP] scrambled according to a scrambling key, a module [CM] for calculating an unscrambling key [Kp] disposed on said dedicated hardware part [HW] and intended to manipulate data under the control of a so-called calculation program stored on said dedicated hardware part [HW], a processor [CPU] for in particular controlling the functioning of the unscrambling [DSC] and calculation [CM] modules. Said system also includes a read only memory [SME] disposed on said dedicated hardware part [HW] for storing a secret key [Kp]. Said calculation program includes instructions for prompting said calculation module [CM] to use said secret key [L] and at least one data item [AC[n,p] or Kpc)] coming from outside the secure data processing system, in order to calculate an unscrambling key [Kp].

Abstract: The invention relates to a method for cryptographic authentication in access security systems. The aim of the invention is to provide a software solution. To this end, the method for secured storage of counter states in a non-volatile memory (EEPROM) (10) involves an incrementing (11) process, and the current counter state is updated in only one EEPROM segment following each incrementing process (11), a subsequent access to the EEPROM (10) only being enabled in the event of a successful incrementing (11) of an EEPROM-based counter.

Abstract: A signal processing circuit comprising a sigma delta analog to digital converter with a feedback loop that comprises an analog filtering circuit (14) that has a controllable time constant. In a calibration mode a detector (18) detects a signal strength in a band (34) of frequencies at an output of the sigma delta analog to digital converter. A bandwidth control circuit (19) has an output coupled to a control input of the analog filtering circuit (14), and is arranged to control said time constant dependent on a signal strength in a band (34) of frequencies at the output of the sigma delta analog to digital converter. The band (34) of frequencies is selected so that noise shaped quantization noise density (32) of the sigma delta analog to digital converter rises with frequency. Thus, detection output depends on the time constant, shifts in the time constant affecting the rise of quantization noise. In this way a simple calibration of the time constant can be realized.

Abstract: A multiphase divider comprises several differential latches connected in a ring. The number of latches in the ring is equal to the number of phases produced and the divisor applied to the input clock. The differential Q-outputs of one latch stage are connected to the corresponding differential D-inputs of the next latch stage. For even numbers of latch stages, the differential clock inputs of each are connected together and alternately to the divider clock input and its complement. The last differential Q-output is returned and cross-connected to the differential D-inputs of the first latch stage. For odd numbers of latch stages, the differential clock inputs of each are respectively connected in parallel to the divider clock input and its complement. The last differential Q-output is returned and straight-connected to the differential D-inputs of the first latch stage.

Abstract: In a global motion estimation, profiles (Prof1, Prof2, ProO, Prof4) are determined of frames (FR1, FR2, FR3, FR4) of an input video signal. Each profile comprises a value, for each pixel in a first direction of the frame, which is obtained by combining pixels in a second direction of the frame. The profiles are updated (Upd Prof) with a first shift (?x?12, ?x?2, ?x?34) to obtain updated profiles (Prof1?, Prof?, Pro3?, and the updated profiles are matched (S/M) to obtain a secondary shift (?x?12, ?x?23). Preferably, the first shift is a zero shift. The updating may be effected by shifting one of the profiles over the first shift to obtain a shifted profile, and subtracting another one of the profiles from the shifted profile. If the second direction is the vertical direction, the profile may comprise a vertically combined (e.g. averaged) pixel value for each pixel in the horizontal direction.

Abstract: This invention concerns novel labeling reactants based on azacycloalkanes, wherein a suitable group is linked to the molecule allowing introduction of the said molecules to bioactive molecules in solution or on solid phase.

Abstract: A wafer (W) comprises at least one die (D1-D6) comprising first (P1) and second (P2) complementary signal processing parts, scribe lanes (SL) defined between and around each die, and coupling means (CM) defined in at least a part of the scribe lanes (SL) and connecting i) the first part output of one of the dies (D1) to a second part input of at least one of the dies (D2) so that the first part output feeds the second part input with first output signals when it is fed with first input signals and configured to work, and so that the output of the fed second part (P2) delivers second output signals when it is configured to work, and/or ii) the second part output of one of the dies (D1) to a first part input of at least one of the dies (D2) so that the second part output feeds the first part input with second output signals when it is fed with second input signals and configured to work and so that the output of the fed first part (P1) delivers first output signals when it is configured to work.

Abstract: A semi-conductor device (100) comprises an exposed leadframe (10) with a die pad (11) and a plurality of leads (12). The die pad (11) has a substantially flat bottom surface (14) and a top surface (15). A semi-conductor die (2) is attached to a die attachment portion (31) of the top surface (15). Downbonds (5) connect the die (2) to a downbond attachment portion (32). Standard bonds (4) connect the die (2) to the leads (12). A plastic package (6) encapsulates the die (2), the standard bonds (4) and the downbonds (5). The top surface of the die pad has portions located at different levels, and step-shaped transitions between two adjacent ones of such portions. At least one of such step-shaped transition (36) is located between the die (2) and the downbonds (5). It has been found that such step-shaped transition provides good protection against downbond failure.

Abstract: The invention relates to a method and device for generating a panoramic image (3) from a video sequence composed of several consecutive images (I0, I1, Ik?1, Ik). The method comprises the following successive steps: —receiving on an input (4) a current image (I1, Ik) having a first and a second portions (40, 42); —if the pixel of the current image is associated to components resulting from a weighted sum of components stem from a number of images lower than a predefined threshold (N), computing components resulting from the weighted sum of components associated to the identified pixel of the current image (I1, Ik) and of components associated to the corresponding pixel of a so-called previous mix image.

Abstract: A thin-film bulk acoustic wave (BAW) resonator, such as SBAR or FBAR, for use in RF selectivity filters operating at frequencies of the order of 1 GHz. The BAW resonator comprises a piezoelectric layer (14) having first and second surfaces on opposing sides, a first electrode (16) extending over the first surface, and a second electrode (12) extending over the second surface, the extent of the area of overlap (R1) of the first and second electrodes determining the region of excitation of the fundamental thickness extensional (TE) mode of the resonator. The insertion loss to the resonator is reduced by providing a dielectric material (18) in the same layer as the first electrode (16) and surrounding that electrode. The material constituting the dielectric material (18) has a different mass, typically between 5% and 15 %, from the material comprising the first electrode (16) it surrounds. The mass of the dielectric material (18) can be lower or higher than the mass of the first electrode (16).

Abstract: A method for adjusting the signal to noise ratio of a receiver comprises measuring the peak power for an RF signal and determining, based on the measured peak power, whether the RF signal power is within a desired operating range. The method further includes adjusting an RF attenuation for the receiver, when it is determined that the RF signal power is not within the desired operating range. The method further comprises measuring a peak power for an IF signal, determining based on the measured peak power, whether the IF signal power is within a desired operating range, and adjusting an IF attenuation for the receiver, when it is determined that the IF signal peak power is not within the desired operating range.

Abstract: An input signal is compared to 2N?1 reference voltages to generate 2N?1 corresponding binary valued comparison signals, delaying at least one of the comparison signals by a variable delay and detecting a difference in arrival time between the delayed signal and another comparison signal. A time interpolation signal encoding a plurality of bins within a least significant bit quantization level is generated, based on the detected difference in arrival time. An M-bit output data is generated based on the comparison signals and the time interpolation signal. A non-uniformity of a code density of the M-bit output data is detected, and based on the detecting the delaying is varied.

Abstract: A quadrature modulator and a method of calibrating same by applying a first test tone signal to an in-phase modulation branch input of the modulator and a ninety degree phase-shifted version of the first test tone signal to a quadrature modulation branch input of the modulator. The carrier leakage level in an output signal of the modulator is measured and in response base band dc offset voltages are adjusted to minimize the carrier leakage. A second test tone signal is applied to the in-phase modulation branch input and a ninety degree phase-shifted version of the second test tone signal to the quadrature modulation branch input. The level of an undesired upper sideband frequency component in the output signal is measured and in response base band gains the in-phase and quadrature modulation branches and a local oscillator phase error are adjusted to minimize the undesired sideband.

Abstract: Systems and methods are provided. In this regard, a representative system incorporates a crystal oscillator circuit and a digital automatic level control circuit. The digital automatic level control circuit is operative to: convert an oscillation amplitude of the crystal oscillator circuit to a proportional DC voltage; convert the DC voltage to a corresponding digital code representation; and adjust bias current and oscillator loop gain such that a desired oscillation amplitude is set.