Abstract: A wireless station (102) connecting nodes via a wireless network. The wireless station has a programmable physical layer (204) physically connected to communicate with at least one local node (142); and a controller (212) configured to detect at least one remote node (134) over the wireless network and enable communications between the local node and the remote node. Also there is a wireless network (105) having multiple nodes capable of wirelessly connecting the nodes to the network, having a first wireless station (102) capable of representing more than one remote node and having a programmable 1394 Standard physical layer, the first wireless station physically connected to at least one local node (142) and representing at least one remote node to the local node and a controller (212) configured to detect at least one remote node and enable communications between the local node and the remote node.

Abstract: An integrated HF-amplifÊer structure comprises in a first direction (FD) in the order mentioned: an input bond pad (IBP), a plurality of cells (CE1, CE2) being displaced with respect to each other in the first direction (FD), and an output bond pad (OBP). Each one of the cells (CE1, CE2) comprises an amplifier having an input pad (GP1, GP2), an active area (A1, A2), and an output pad (DP1, DP2). The active area (A1, A2) is arranged in-between the input pad (GP1, GP2) and the output pad (DP1, DP2), and the input pad (GP1, GP2), the active area (A1, A2), and the output pad (DP1, DP2) are displaced with respect to each other in a second direction (SD) substantially perpendicular to the first direction (FD). A first network (N1) comprises first interconnecting means (Li, Ci; Li1, Li2, Ci1) to interconnect input pads (GP1, GP2) of adjacent ones of the plurality of cells (CE1, CE2), and extends in the first direction (FD).

Abstract: The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region (1,2,3) first conductivity type, a second conductivity type opposite to said first conductivity type and the first conductivity type, respectively, with a first semiconductor region (3) comprising the collector region or the emitter region being formed in the semiconductor body (11), on top of which a second semiconductor region (2) comprising the base region is present, on top of which a third semiconductor region (1) comprising the other of said collector region and said emitter region is present, said semiconductor body (11) being provided with a constriction at the location of the transition between the first and the second semiconductor region (3, 2), which constriction has been formed by means of an electrically insulating region (26, 27) buried in the semiconductor body (11).

Abstract: In order to further develop a circuit arrangement (100) as well as a corresponding method for voltage reference and/or for current reference in such circuit arrangement (100) in such way that any additional reference to observe the bandgap reference is not required, it is proposed to perform at least one analog built-in self test (BIST) scheme on the basis of the output of the bandgap reference.

Abstract: A data processing system for processing at least one application is provided. The data processing system comprises a processor (100) for executing the application. The system furthermore comprises a cache memory (200) being associated to the processor (100) for caching data and/or instructions for the processor (100). The system furthermore comprises a memory unit (400) for storing data and/or instructions for the application. The memory unit (400) comprises a plurality of memory partitions (401-404). Data with similar data attributes are stored in the same memory partition (401-404). A predefined prefetching pattern is associated to each of the memory partitions (401-404).

Abstract: The invention relates to a method and a system for testing a wireless network device (1) connected to a communication channel (3), whereby:—a testing computer (2) connected to the communication channel (3) starts a test function;—the wireless network device (1) starts a unifying testing module being adapted to a hardware constellation of said wireless network device (1) and/or an operating system running on said wireless network device (1) and providing an application programming interface connected to said communication channel (3) and being independent of said hardware constellation and/or said operating system;—said test function sends at least one command to said unifying testing module at least via said communication channel (3) and said application programming interface; and—said unifying testing module executes said command from the test function and sends at least a status of execution of said command back to the test function at least via the application programming interface and said communication c

Abstract: A device for generating an output clock signal intended to time a digital processing circuit, said generating device receiving a first clock signal, characterized in that it comprises an oscillator generating a second clock signal constituting said output clock signal, said oscillator functioning in a forced mode under the control of the rising and falling edges of said first clock signal, said oscillator functioning in a free mode in the absence of rising or falling edges in said first clock signal, the natural frequency of said oscillator being lower than the frequency of said first clock signal.

Abstract: A device is for digitally processing an input signal that is susceptible to variations in signal strength. The signal (48) is analog to digital converted into a bitstream signal (47), the bitstream signal representing the input signal by consecutive digital values. The device has a signal strength detection circuit (32) for generating a control signal indicative for an overload condition in which the signal strength exceeds a input range of the analog to digital converter, e.g. a sigma-delta modulator. The signal strength detection circuit detects, in the bitstream signal, a sequence (49,50) of adjacent and equal digital values, the sequence having at least a predetermined length. The circuit detects the overload condition effectively and fast, avoiding the delay of signal strength detection in a digital processor.

Abstract: A system and method for fabricating integrated circuits using four fine alignment targets per stepper shot. The four alignment targets are disposed within the scribe line on each side of a four-sided stepper shot. The targets on opposites sides of the region are located in mirror-image positions. For example, in a square or rectangular region, the targets could be at the mid-point of each side, or at each corner. Because the scribe lines for adjoining stepper shots overlap, a target in one shot will overlay a target from a preceding shot. In a positive resist process, for example, the target resulting from the overlay will be reduced in size by an amount corresponding to the amount of rotational error, if any. However, the target will still indicate the center of the stepper shot, thereby compensating for the rotational error with no further measurements.

Abstract: In photo-lithography, one may assess the effect of flare due to various exposure tools. In an example embodiment, in a photo-lithography process on a photo resist coated substrate, there is a method (600) for determining the effect of flare on line shortening. The method (600) comprises, at a first die position on the substrate and in a first exposure, printing a first mask (610) that includes a flare pattern (110) corresponding to one corner of the first mask (610), and in a second exposure, printing a second mask (620) that includes another flare pattern corresponding to an opposite corner of the second mask. At a second die position on the substrate, a composite mask pattern (630) based on features of the first mask and the second is printed. The printed patterns (640) are developed and measurements (650) are obtained therefrom. The effect of flare (660) is determined as a function of the measurements.

Abstract: In order to further develop a circuit arrangement (100), in particular to a phase-locked loop for sub-clock or sub-pixel accurate phase-measurement and phase-generation, as well as a corresponding method in such way that no clock multiplier phase-locked loop is to be provided behind the time-to-digital converter and that neither an analog delay line nor a signal divider unit is to be provided between the digital ramp oscillator or discrete time oscillator and the digital-to-time converter, wherein less analog circuitry is susceptible for noise and for ground bounce in the digital environment, it is proposed to provide at least one phase measurement unit (10);—at least one loop filter unit (40; 40?) being provided with at least one output signal (delta-phi) of at least one phase detector unit (30); at least one digital ramp oscillator unit or discrete time oscillator unit (50; 50?) being provided with at least one output signal, in particular with at least one increment (inc), of the loop filter unit (40; 40?)

Abstract: An analog-to-digital converter circuit comprises a first voltage comparator coupled to a first reference voltage and a signal voltage, the first voltage comparator having first negative and first positive outputs for outputting a comparison of the first reference voltage with the signal voltage; a second voltage comparator coupled to a second reference voltage and the signal voltage, the second reference voltage different than the first reference voltage, the second voltage comparator having second negative and second positive outputs for outputting a comparison of the second reference voltage with the signal voltage; and a first arrival time comparator coupled to the first positive output and the second negative output, the first arrival time comparator having a first arrival time comparator output for outputting a comparison of the first positive output with the second negative output.

Abstract: A method and apparatus for compressing test vector data for use in testing a logic product, wherein original test vector data is generated in the form of two or more sequences of bits including “care” bits and “don't care” bits. The test vector data is then compressed by comparing corresponding bits of two or more subsequent vectors and merging the two or more vectors into a single vector representative thereof if all of the corresponding bits of the two or more vectors are found to be compatible. Compatibility of two bits is achieved if they do not have specifically incompatible or opposite values.

Abstract: An access point (AP) (120a) manages and coordinates the switching of mobile devices (110) to other access points (120b, c, d). The access point (120a) monitors the quality of its communications link with the mobile device (110). When the access point (120a) determines that the quality is degrading, or when the access point (120a) determines that its traffic is excessive, or when another switch-triggering event (202) occurs, the access point (120a) sends a transfer-request to other access points (120b, c, d) in its vicinity. If another access point can accept the mobile device (110), it notifies the requesting access point (120a) that it is available. The requesting access point (120a) selects from among the available access points (120b, c, d), and notifies the mobile device (110) to switch to the selected access point.

Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.

Abstract: A method of making a FET includes forming a gate structure (18), then etching cavities on either side. A SiGe layer (22) is then deposited on the substrate (10) in the cavities, followed by an Si layer (24). A selective etch is then carried out to etch away the SiGe (22) except for a part of the layer under the gate structure (18), and oxide (28) is grown to fill the resulting gap. SiGe source and drains are then deposited in the cavities. The oxide (28) can reduce junction leakage current.

Abstract: The present invention relates to transmitter devices and transmission methods of transmitting a modulated GMSK- or EDGE-signal in a transmission system, wherein normally the pulse shaping follows the given rules of standards for these mobile radio systems. The amount of TX spectra in the adjacent TX channels is predetermined by these rules. A second filtering step is suggested to be introduced for attenuating predetermined unwanted spectra in the adjacent transmit channels. A second goal of this suggestion is to reduce spectra at adjacent TX channels also at cases of nonlinearity at the TX Power Amplifier of the RF transmitter Nothing must be changed in standards of mobile communication systems, for example GSM.

Abstract: A graphics pipeline (20) for rendering graphics receives texture data (22) and vertex data (23). The texture data (22) define-rectangular texture maps (24), which are axis-aligned in texture space. The vertex data (23) describe output quadrilaterals (25) in screen space. A rasterizer (27) rasterizes the input rectangle (24) by determining which texels are inside the input rectangle (24). A mapper (28) maps the texels inside the input rectangle (24) onto the output quadrilaterals (25). The mapping is performed by calculating screen space output coordinates from the texture space grid coordinates of the texels. For the calculation an equation is used comprising at least one linear combination of the texture space grid coordinates of the texels inside the input rectangles (24) and at least one product of real powers of the texture space grid coordinates of the texels inside the input rectangles (24).

Abstract: A device (1) comprising a sensor module (2) with a package (3) is produced at reduced costs by providing the package (3) with two or more substrates (4,5) each with a functional layer (14,15), at least one sensor (24,25) such as a magnetometer and/or an accelerometer being located in at least one functional layer (14,15), and by providing the package (3) with a system comprising solder bumps (7-12) for aligning the functional layers (14,15).

Abstract: A data processing system according to the invention comprising a group of at least a first and a second module, wherein each module has a data processing facility, a clock for timing data transmissions from the module to another module, a time-slot counter for counting a number of time slots which are available for transmission of data. The modules have a first operational state wherein the counted number of time slots is less than or equal to a predetermined number, in which operational state data transmission is enabled, and a second operational state wherein the number is in excess of the predetermined number, in which second operational state data transmission is disabled, Each module has a notifying facility for notifying when it is in the second operational state.