Patents Assigned to NXP
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Patent number: 7548591Abstract: A quadrature modulator and a method of calibrating same by applying a first test tone signal to an in-phase modulation branch input of the modulator and a ninety degree phase-shifted version of the first test tone signal to a quadrature modulation branch input of the modulator. The carrier leakage level in an output signal of the modulator is measured and in response base band dc offset voltages are adjusted to minimize the carrier leakage. A second test tone signal is applied to the in-phase modulation branch input and a ninety degree phase-shifted version of the second test tone signal to the quadrature modulation branch input. The level of an undesired upper sideband frequency component in the output signal is measured and in response base band gains the in-phase and quadrature modulation branches and a local oscillator phase error are adjusted to minimize the undesired sideband.Type: GrantFiled: April 20, 2004Date of Patent: June 16, 2009Assignee: NXP B.V.Inventors: Ali Parsa, Ali Fotowat-Ahmady, Ali Faghfuri, Mahta Jenabi, Emmanuel Riou, Wilhelm Steffen Hahn
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Publication number: 20090150467Abstract: A method of generating a pseudo-random number by means of an iteration, comprising at least two iteration steps, applied to a one-way function, wherein the one-way function, based on a start value and a key, generates part of the pseudo-random number and wherein the iteration is initialized with a random start value and a random key, and wherein, in each iteration step, both the start value and the key for an iteration step are determined from the part of the pseudo-random number determined in the previous iteration step using the one-way function.Type: ApplicationFiled: October 10, 2006Publication date: June 11, 2009Applicant: NXP B.V.Inventors: Heike B. Neumann, Steffen Scholze, Matthias Voegeler
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Publication number: 20090145215Abstract: A measuring method for measuring physical variables comprises the selection of a working point (AP) lying within a total measurement range (G) of a physical variable (M) to be measured, the detection of a measured value (M(t1)) of the physical variable at a first measuring time (t1), the determination of a displacement value (V(t1)) as the result of a subtraction of the measured value (M(t1)) measured at the first measuring time from the working point (AP), the formation of change values (C(t2), C(t3) . . . C(tx)) of the physical variable (M) by acquiring subsequent measured values (M(t2), M(t3) . . . M(tx)) of the physical variable at subsequent measuring times (t2, t3 . . . tx) and addition of the displacement value (V(t1)) to the subsequent measured values.Type: ApplicationFiled: February 10, 2009Publication date: June 11, 2009Applicant: NXP B.V.Inventor: Bernhard Georg SPIESS
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Publication number: 20090147957Abstract: This invention provides for a transaction card for use at a terminal and for initiating an internet transaction with a SSL protected server, wherein the card comprises a smartcard including an application arranged for extending an SSL connection from the said protected server into the smartcard and, further, the invention can provide for a related terminal, server and related transaction initiation and establishment methods, for extending the said SSL connection as noted above.Type: ApplicationFiled: May 15, 2007Publication date: June 11, 2009Applicant: NXP B.V.Inventor: Bruce Murray
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Publication number: 20090148966Abstract: A system in package (10) has a, preferably wireless, test controller (20) for testing each die (30) after it has bee mounted onto the substrate of the system in package (10), and a faulty die (30) is repaired before a next die (30) is mounted onto the substrate (15). This way, the system in package (10) can be tested during the intermediate stages of its manufacturing, thus ensuring that all dies (30) function correctly before sealing the dies in the single package. Consequently, a method for manufacturing a system in package (10) is obtained that has an improved yield compared to known manufacturing methods.Type: ApplicationFiled: July 18, 2006Publication date: June 11, 2009Applicant: NXP B.V.Inventors: Philippe L. L. Cauvet, Herve Fleury, Fabrice Verjus
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Publication number: 20090146760Abstract: The chip (100) comprises a network of trench capacitors (102) and an inductor (114), wherein the trench capacitors (102) are coupled in parallel with a pattern of interconnects (113A,B, . . . ) that is designed so as to limit generation of eddy current induced by the inductor (114) in the interconnects (113A,B, . . . ). This allows the use of the chip (100) as a portion of a DC-DC converter, that is integrated in an assembly of a first chip and this—second chip (100). The inductor of this integrated DC-DC converter may be defined elsewhere within the assembly.Type: ApplicationFiled: May 14, 2007Publication date: June 11, 2009Applicant: NXP B.V.Inventors: Derk Reefman, Roozeboom Freddy, Johan H. Klootwijk
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Publication number: 20090150468Abstract: A FIR filter (20) has a delay line comprising four delay elements (21a, 21b, 21c, 21d) for delaying a signal received at a filter input (22) and four multipliers (24a, 24b, 24c, 24d) for multiplying the delayed signals by respective partial filter coefficients a, b, c, d. The delay elements (21a, 21b, 21c, 21d) and multipliers (24a, 24b, 24c, 24d) are connected alternately in series. Four taps (23a, 23b, 23c, 23d) extract the signal from the delay line immediately after each of the delay elements (21a, 21b, 21c, 21d) and output the delayed, multiplied signals to an adder (25) for adding the delayed, multiplied signals to generate a filter output (26). The partial filter coefficients a, b, c, d effectively combine to implement filter coefficients A, B, C, D for the taps (23a, 23b, 23c, 23d), e.g. with A=a, B=a*b, C=a*b*c and D=a*b*c*d.Type: ApplicationFiled: July 26, 2006Publication date: June 11, 2009Applicant: NXP B.V.Inventor: Robert Fifield
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Patent number: 7544998Abstract: A Silicon on Insulator device is disclosed wherein a parasitic channel induced in a thin film portion of the device is prevented from allowing current flow between the source and drain by a Deep N implant directly below the source or drain. The deep N implant prevents a depletion region from being formed, thereby cutting off current flow between the source and the drain that would otherwise occur.Type: GrantFiled: June 8, 2004Date of Patent: June 9, 2009Assignee: NXP B.V.Inventor: Theodore Letavic
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Patent number: 7545026Abstract: An electronic device (ICD) comprises a signal ground contact (LD1) for coupling the electronic device to signal ground, a die pad, and an integrated circuit. The die pad (DPD) is provided with a protrusion (PTR3) that is electrically coupled to the signal ground contact. The integrated circuit (PCH) has a contact pad (GP2) that faces the protrusion of the die pad and that is electrically coupled thereto.Type: GrantFiled: July 6, 2005Date of Patent: June 9, 2009Assignee: NXP B.V.Inventor: Jean-Claude G. Six
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Patent number: 7545853Abstract: A method of acquiring a received spread spectrum signal, especially a GPS signal, is disclosed together with a spread spectrum signal receiver and a cellular telephone incorporating such a receiver. The method comprises the steps of: providing a replica signal containing a pseudorandom noise code, corresponding to that of the spread spectrum signal; providing a subject signal containing two fragments of the spread spectrum signal initially received during respective time periods between which a further time period elapses; and coherently correlating the replica signal with the subject signal over the two fragments.Type: GrantFiled: September 6, 2004Date of Patent: June 9, 2009Assignee: NXP B.V.Inventors: Iwo-Martin Mergler, Andrew T. Yule, Saul R. Dooley
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Patent number: 7546474Abstract: In a bus system with a low-power phase, in which bus members are in a state of reduced current consumption and leave this state when the bus lines (1, 2) are active for a longer period than a predetermined time interval, the function of the bus in the low-power phase is monitored in that a first participant (3) cyclically transmits at least one pulse on the bus during the low-power phase, which pulse has a duration that is shorter than the predetermined time interval and is received and evaluated at least by a second bus member (4) for the purpose of monitoring the bus lines (1, 2).Type: GrantFiled: December 21, 2001Date of Patent: June 9, 2009Assignee: NXP B.V.Inventor: Matthias Muth
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Publication number: 20090141777Abstract: Stations like mobile terminals, bases stations and network nodes comprising rake receivers with fingers require relatively many calculations to be performed for despreading a symbol. By replacing despreading multipliers, integrators and dumpers in the fingers by Hadamard transformers (62), chips of several symbols with orthogonal channelization codes can be despreaded simultaneously, and the station and the rake receiver have become more efficient. The despreading section (60 of the finger (34) comprises the Hadamard transformer (62) and a serial-to-parallel converter (61) comprising downsamplers (71-73). The station is a high-speed downlink packet access station (HSDPA) in a universal mobile telecommunication system (UMTS), with a number of de-channelization codes used being at least ten percent of a despreading factor used.Type: ApplicationFiled: January 23, 2009Publication date: June 4, 2009Applicant: NXP B.V.Inventor: Frank Heinle
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Publication number: 20090144445Abstract: In order to provide a method for transmitting messages between a number of nodes (1, 2, 3, 4) of a network over two channels (A, B) which ensures reliable message transmission even in the event of a failure of one of the two channels (A, B), it is proposed that, in the event of a failure of one channel (A, B), messages are transmitted over the other channel (B, A).Type: ApplicationFiled: July 31, 2006Publication date: June 4, 2009Applicant: NXP B.V.Inventors: Andries Van Wageningen, Peter Fuhrmann
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Patent number: 7542041Abstract: A multiple-pipeline system (300) includes a pool (330) of auxiliary function blocks (A-E 335) that are provided as required to select pipelines. Each pipeline (320) in the multiple-pipeline system (300) is configured to include a homogeneous set of core functions (F1-F6). A pool (330) of auxiliary functions (A-E 335) is provided for selective insertion of auxiliary functions (A-E 335) between core functions (F1-F6) of select pipelines. Each auxiliary function includes a multiplexer that allows it to be selectively coupled within each pipeline.Type: GrantFiled: April 2, 2004Date of Patent: June 2, 2009Assignee: NXP B.V.Inventors: Santanu Dutta, Jens Rennert
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Publication number: 20090135306Abstract: A receiver has a tuning capacitance that comprises two capacitive branches (V1-C1, C2-V2) coupled in parallel between a pair of capacitance nodes (N1, N2). One capacitive branch (V1-C1) comprises a varicap diode (V1) having an anode that is coupled to one capacitance node (N1) and a cathode that is coupled to the other capacitance node (N2). The other capacitive branch (C2-V2) comprises a varicap diode (V2) having a cathode that is coupled to the one capacitance node (N1) and an anode that is coupled to the other capacitance node (N2).Type: ApplicationFiled: March 16, 2006Publication date: May 28, 2009Applicant: NXP B.V.Inventors: Kui Y. Lim, Joe K. K. Leong
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Publication number: 20090134904Abstract: An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores.Type: ApplicationFiled: October 20, 2006Publication date: May 28, 2009Applicant: NXP B.V.Inventors: Amir Zjajo, Hendrik J. Bergveld, Rodger F. Schuttert, Jose De Jesus Pineda De Gyvez
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Patent number: 7539045Abstract: Magnetic or magnetoresistive random access memories (MRAMs) are implemented in a variety of arrangements and methods. Using one such arrangement, a matrix is implemented with magnetoresistive memory cells logically organized in rows and columns, each memory cell including a magnetoresistive element. The matrix has a set of column lines, a column line being a continuous conductive strip which is magnetically coupled to the magnetoresistive element of each of the memory cells of a column, wherein each column line has a forward column line and a return column line arranged on opposite sides of the magnetoresistive element and offset from one another for forming a return path for current in that column line.Type: GrantFiled: November 6, 2003Date of Patent: May 26, 2009Assignee: NXP B.V.Inventor: Hans Marc Bert Boeve
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Patent number: 7539614Abstract: In a sound reproduction or recording system an audio signal is multiplied by a gain factor (z) which is dependent on the input level (y). The dependence of the gain factor on input level is chosen such that unvoiced phonemes are at least 6 dB, preferably at least 12 dB more enhanced than voiced phonemes, where preferably the average gain is less than 6 dB. This improves the intelligibility.Type: GrantFiled: May 17, 2004Date of Patent: May 26, 2009Assignee: NXP B.V.Inventor: Christophe Marc Macours
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Patent number: 7539879Abstract: A circuit arrangement and method of controlling power dissipation utilize a register file (60) with power dissipation control capabilities through a banked register design coupled with enable logic (62, 82) that is configured to selectively disable unused banks (70) of registers by selectively gating off clock (74), address (76) and data (78) inputs supplied thereto.Type: GrantFiled: December 3, 2003Date of Patent: May 26, 2009Assignee: NXP B.V.Inventors: Andrei Terechko, Manish Garg
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Patent number: 7538337Abstract: Semiconductor devices may be fabricated using nanowires. In an example embodiment, a conductive gate may be used to control conduction along the nanowires, in which case one of the contacts is a drain and the other a source. The nanowires may be grown in a trench or through-hole in a substrate or in particular in an epitaxial layer on substrate. In another example embodiment, the gate may be provided only at one end of the nanowires. The nanowires can be of the same material along their length; alternatively different materials can be used, especially different materials adjacent to the gate and between the gate and the base of the trench.Type: GrantFiled: June 7, 2005Date of Patent: May 26, 2009Assignee: NXP B.V.Inventors: Erwin A. Hijzen, Erik P. A. M. Bakkers, Raymond J. E. Hueting, Abraham R. Balkenende