Patents Assigned to NXP
-
Patent number: 7538337Abstract: Semiconductor devices may be fabricated using nanowires. In an example embodiment, a conductive gate may be used to control conduction along the nanowires, in which case one of the contacts is a drain and the other a source. The nanowires may be grown in a trench or through-hole in a substrate or in particular in an epitaxial layer on substrate. In another example embodiment, the gate may be provided only at one end of the nanowires. The nanowires can be of the same material along their length; alternatively different materials can be used, especially different materials adjacent to the gate and between the gate and the base of the trench.Type: GrantFiled: June 7, 2005Date of Patent: May 26, 2009Assignee: NXP B.V.Inventors: Erwin A. Hijzen, Erik P. A. M. Bakkers, Raymond J. E. Hueting, Abraham R. Balkenende
-
Patent number: 7537969Abstract: A fuse structure (100) suitable for incorporation in an integrated circuit presents a reduced thermal conduction footprint to the substrate (103). A patterned material stack (102) is formed on a substrate (103) and at least a portion of a material disposed between the substrate (103) and an upper portion of the fuse structure (100) is selectively etched so as to reduce the thermal conduction pathway between the upper portion and the substrate (103). In a further aspect of the present invention, the reduced cross-section of the fuse structure (100) has an increased current density resulting in a lower amount of current being needed to program the fuse.Type: GrantFiled: September 18, 2004Date of Patent: May 26, 2009Assignee: NXP B.V.Inventors: Piebe Zijstra, Ann Killian
-
Patent number: 7537939Abstract: In the manufacture of semiconductors, it is often necessary to characterize the effect of line width and line width shape on yield. In an example embodiment, there is a method (200) for randomizing exposure conditions across a substrate. The method comprises generating a list of random numbers (210). A random number is mapped (220) to an exposure field, forming a list of random numbers and corresponding exposure fields. The list or random numbers and corresponding exposure fields is sorted (230) by random number. To each exposure field in the list sorted by random number, an exposure dose is assigned (240). The list is sorted is sorted by exposure field (250).Type: GrantFiled: April 27, 2004Date of Patent: May 26, 2009Assignee: NXP B.V.Inventors: David Ziger, Steven Qian
-
Patent number: 7538443Abstract: A system and method for identifying misalignments in an overlapping region of a stitched circuit in an integrated circuit fabrication process. The method comprises: creating a first circuit using a reference mask, wherein first circuit includes a first part of an offset dependent resistor structure in the overlapping region; creating a second circuit using a secondary mask, wherein the second circuit includes a second part of the offset dependent resistor structure in the overlapping region, wherein the offset dependent resistor structure includes a plurality of nubs that interconnect the first part and the second part of theis offset dependent resistor structure; measuring a resistance across the offset dependent resistor structure; and determining an amount of misalignment based on the measured resistance.Type: GrantFiled: June 25, 2004Date of Patent: May 26, 2009Assignee: NXP B.V.Inventor: Joseph M. Amato
-
Patent number: 7539588Abstract: A circuit has a first memory for modifiable storage of information, the information being modifiable by an ambient parameter of the circuit, which ambient parameter acts on the first memory. The first memory includes a test memory area for storing test information. The circuit also includes a second memory for unmodifiable storage of reference information and a detection circuit. The test information and reference information is supplied to the detection circuit. The detection circuit then detects whether a modification of the originally stored test information has been brought about by an ambient parameter acting on the first memory.Type: GrantFiled: May 16, 2003Date of Patent: May 26, 2009Assignee: NXP B.V.Inventors: Martin Posch, Helmut Haar
-
Patent number: 7538570Abstract: An integrated circuit is provided with a distributed supply voltage monitoring system in which a single controller controls a plurality of voltage monitors located in respective modules of the integrated circuit. The controller and each circuit form a successive approximation analogue to digital converter Such a system enables a small size monitoring circuit to be realized for every module of the integrated circuit.Type: GrantFiled: April 20, 2006Date of Patent: May 26, 2009Assignee: NXP B.V.Inventors: Marcel Pelgrom, Violeta Petrescu, Hendrickus Joseph Maria Veendrick
-
Patent number: 7539118Abstract: A multitrack optical disc reader (1) is disclosed comprising a multitrack optical pick up (11) for reading data from multiple tracks of an optical disc (10) and outputting the data from each track in respective data streams, and multiple first-in-first-out (FIFO) memories (21) for temporarily storing the data streams. In accordance with the present invention, wherein the pickup may selectively output data streams from less than the maximum number of tracks that can be read by the pickup, the multiple FIFO memories are provided in a common memory bank, and when less than the maximum number of tracks are being read by the pickup, the size of at least one FIFO memory in use is greater than the total available FIFO memory in the common memory bank divided by the maximum number of tracks that can be read by the pickup.Type: GrantFiled: April 3, 2003Date of Patent: May 26, 2009Assignee: NXP B.V.Inventor: Arougg Jbira
-
Patent number: 7539276Abstract: In accordance with the present invention, a method of processing a sampled signal stream containing at least one spread spectrum signal is provided together with a receiver, computer, computer-readable storage medium and computer program for the same. The method comprises the steps of processing samples at a first bit level and, either in parallel or subsequently, processing samples at a second bit level, different from the first bit level.Type: GrantFiled: July 30, 2004Date of Patent: May 26, 2009Assignee: NXP B.V.Inventors: Saul R. Dooley, Andrew T. Yule
-
Patent number: 7537384Abstract: In a temperature-recording method for recording a temperature by means of an electrical circuit of a data storage medium, which electrical circuit is suppliable with energy by means of a signal feedable to the data storage medium, provision is made for a physical variable dependent on the temperature to be recorded by means of the circuit supplied with energy, the physical variable being influenced by a temperature-recording material (1, 7), preferably a piezoelectric or ferroelectric material, co-operating with the circuit, which material comprises alignable electric or magnetic elementary dipoles (3), and for which temperature-recording material (1, 7) a Curie temperature is known, exceeding of which causes the alignment of the elementary dipoles to be lost, and the temperature-recording material (1, 7) being selected in such a way that its known Curie temperature corresponds to a pre-determined limit temperature.Type: GrantFiled: May 17, 2005Date of Patent: May 26, 2009Assignee: NXP B.V.Inventor: Achim Hilgers
-
Patent number: 7539391Abstract: A method for trick-mode play of an encrypted transport stream containing audio/video/data information comprising: extracting and decrypting data used as local metadata for programs in the encrypted transport stream; creating trick-mode pointers from the metadata; and storing the trick-mode pointers and the encrypted transport stream on a storage medium.Type: GrantFiled: June 27, 2002Date of Patent: May 26, 2009Assignee: NXP B.V.Inventors: Alan P. Cavallerano, Richard Chi-Te Shen
-
Publication number: 20090127553Abstract: A wafer (W) comprises i) at least one independent die (D1, D2) having internal integrated components (IC), a multiplicity of internal pads (IP1-IP3) connected to some of the internal integrated components (IC), ii) scribe lanes (SL) defined between and around each independent die (Di), and in part of which are defined, for each die (D1, D2), at least a first group (G11, G12) of external pads (EP1-EP3) and/or a second group of external test integrated components (EC). The external pads (EP1-EP3) of each first group (G11, G12) are connected, through conductive tracks, to a chosen one of the internal pads (IP1-IP3) and/or internal integrated components (IC) of the associated die (D1, D2), and arranged to be fed with chosen test signals or to collect test result signals. Each external test integrated components of each second group is connected, through conductive tracks, to a chosen one of the die internal pads and/or die internal integrated components (IC) and/or to external pads of a first group.Type: ApplicationFiled: September 25, 2006Publication date: May 21, 2009Applicant: NXP B.V.Inventors: Herve Marie, Sofiane Ellouz
-
Publication number: 20090132831Abstract: An apparatus and method is provided for protecting data in a non-volatile memory by using an encryption and decryption that encrypts and decrypts the address and the data stored in the non-volatile memory using a code read only memory that stores encryption and decryption keys that are addressed by a related central processing unit at the same time data is being written or read from the non-volatile memory by the central processing unit.Type: ApplicationFiled: May 22, 2008Publication date: May 21, 2009Applicant: NXP B.V.Inventor: WOLFGANG BUHR
-
Publication number: 20090127690Abstract: The present invention relates to A package (50,70) for a microelectronic component, comprising: a carrier element (12) having a first side (16) that comprises conductor lines (14); —a microelectronic component (20) having a first surface (24) and a second surface (23) facing away from the first surface; the microelectronic component with said second surface mounted on said first side and connected to the conductor lines via bonding wires (28); a polymeric encapsulation material (30) encapsulating the bonding wires and exposing a central zone (40) of said first surface (24), the encapsulation material comprising an outer edge (36) at said first side and an inner edge (38) at said first surface; a dam (42,44) abutting to the encapsulation material; wherein the dam (44) comprises a step-shaped surface transition (46) at said first side (16), the surface transition abutting on said outer edge (36).Type: ApplicationFiled: July 13, 2006Publication date: May 21, 2009Applicant: NXP B.V.Inventors: Dandy N. Jaducana, Johnathan S. Catalla, Nhoy Lacson, Jose O. Amistoso
-
Publication number: 20090129190Abstract: A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity.Type: ApplicationFiled: February 28, 2006Publication date: May 21, 2009Applicant: NXP B.V.Inventors: Teunis Jian Ikkink, Pierre Hermanus Woerlee, Victor Martinus Van Acht, Nicolaas Lambert, Albert W. Marsman
-
Publication number: 20090131008Abstract: A receiver comprises a radio frequency splitter (SPL) and respective tuning elements (D11, D21, D31), which are coupled to respective outputs (O1, O2, O3) of the radio frequency splitter One of these tuning elements (D11) has a control terminal coupled to receive a direct current control signal (VA) via a radio frequency-blocking circuit (R11, L11). A direct current path (R1, L1) extends, via the radio frequency splitter, from the aforementioned control terminal to a control terminal of another tuning element (D21).Type: ApplicationFiled: April 17, 2007Publication date: May 21, 2009Applicant: NXP B.V.Inventors: Thomas Fenkes, Klaus Bracht
-
Publication number: 20090127615Abstract: A semiconductor device is formed by forming a second trench 120 at the base of a first trench 18, depositing insulator 124 at the base of the second trench 120, and then etching cavities 26 laterally from the sidewalls of the second trench, but not the base which is protected by insulator 124. The invention may in particular be used to form semiconductor devices with cavities under the active components, or by filling the cavities to form silicon on insulator or silicon on conductor devices.Type: ApplicationFiled: April 12, 2006Publication date: May 21, 2009Applicant: NXP B.V.Inventor: Jan Sonsky
-
Publication number: 20090130611Abstract: The present invention provides a method of lithographic patterning. The method comprisese: applying to a surface to be patterned a photoresist (18) comprising a polymer resin, a photocatalyst generator which generates a catalyst on exposure to actinic radiation, and a quencher; exposing the photoresist (18) to actinic radiation through a mask pattern (12); carrying out a post-exposure bake; and then developing the photoresist (18) with a developer to remove a portion of the photoresist which has been rendered soluble in the developer. Either the polymer resin is substantially insoluble in the developer prior to exposure to actinic radiation and rendered soluble in the developer by the action of the catalyst, and by the action of the quencher during the bake, or the polymer resin is soluble in the developer prior to exposure to actinic radiation and rendered substantially insoluble in the developer by the action of the catalyst, and by the action of the quencher during the bake.Type: ApplicationFiled: September 5, 2006Publication date: May 21, 2009Applicant: NXP B.V.Inventors: Peter Zandbergen, Jeroen H. Lammers, David Van Steenwinckel
-
Publication number: 20090127537Abstract: An electric device has an electrically switchable resistor (2?) comprising a phase change material. The resistance value of the resistor can be changed between at least two values by changing the phase of the phase change material within a part of the resistor called the switching zone (12?) using Joule heating of the resistor. The device comprises a body (24?) encapsulating the resistor, which body comprises at least two abutting regions (26?, 28?) having different thermally insulating properties. These regions form a thermally insulating contrast with which the dimension of the switching zone can be determined without having to alter the dimensions of the resistor. Such a device can be used in electronic memory or reconfigurable logic circuits.Type: ApplicationFiled: March 21, 2007Publication date: May 21, 2009Applicant: NXP B.V.Inventors: Friso J. Jedema, Karen Attenborough, Roel Daamen, Michael A.A. In 'T Zandt
-
Patent number: 7535385Abstract: A data processing device and adjusting method for adjusting the timing of a higher-rate stream of second data samples derived from a lower-rate stream of first data samples are described. A predetermined one of the first data samples is stored and first predetermined ones of the second data samples derived from the stored predetermined one of the first data samples are skipped to obtain an acceleration of the time base. Then, second predetermined ones of the second data samples following the skipped first predetermined ones of the second data samples are replaced by new second data samples derived from the stored predetermined one of the first data samples.Type: GrantFiled: October 11, 2004Date of Patent: May 19, 2009Assignee: NXP B.V.Inventor: Gerhard Runze
-
Patent number: 7536165Abstract: A direct conversion receiver includes a detector that provides a measure of bias offset that is caused by component mismatches in the direct conversion mixer, and a corrective network that reduces the bias offset based on this measure. The direct conversion mixer demodulates a radio-frequency (RF) input signal via mixing with a local-oscillator (LO) signal to provide a differential baseband output signal. A differential peak detector compares the peak signal value at each side of the mixer's differential output, and a differential integrator averages the difference between these peak signal values to provide the measure of bias offset. The corrective network adds a correction offset to each of the local oscillator local oscillator paths on each of the switching pairs that provide the differential output, but opposite to the local oscillator connections.Type: GrantFiled: July 24, 2002Date of Patent: May 19, 2009Assignee: NXP B.V.Inventor: William Redman-White