Abstract: In a method and an arrangement for assessing the quality of skin print images, and particularly fingerprint images, provision is made for gradients to be formed for the individual picture elements (pixels) of the skin print image, for a mean value to be formed from the gradients of the pixels in one region of the image (tile) at a time, and for similarities in the mean values from tile to tile to form a measure of quality.

Abstract: A data processing device and adjusting method for adjusting the timing of a higher-rate stream of second data samples derived from a lower-rate stream of first data samples are described. A predetermined one of the first data samples is stored and first predetermined ones of the second data samples derived from the stored predetermined one of the first data samples are skipped to obtain an acceleration of the time base. Then, second predetermined ones of the second data samples following the skipped first predetermined ones of the second data samples are replaced by new second data samples derived from the stored predetermined one of the first data samples.

Abstract: In a radio including analog and digital portions, with at least one A/D Convener between the analog and digital portions, and the selectivity of the radio at least partly implemented in the digital domain, an AGC controller sets a first variable gain amplifier (VGA) (302) to low gain upon a determination that a wide-band power estimation exceeds a wide-band threshold. The wide-b and threshold is selected to reduce the occurrence of A/D converter saturation. If the wide-band power estimation is less than the wide-band threshold, then for each VGA (302) in the analog portion, a determination is made whether a narrow band power estimate exceeds a narrow-band threshold, corresponding to that VGA (302), plus a hysteresis value, in which case that VGA (302) is set to low gain; or whether the narrow-band energy estimate is less than the narrow-band threshold minus a hysteresis value, in which case that VGA (302) is set to high gain.

Abstract: A method of determining a value for a particular pixel of a particular image being temporarily located intermediate a first image and a second image is disclosed. The method comprises: computing a first motion vector difference on basis of a first (Dp) and second (Dpp) motion vector of a first motion vector field (D3(x, n?1)) corresponding to the first image; computing a second motion vector difference on basis of a third (Dn) and fourth (Dnn) motion vector of a second motion vector field (D3(x, n)) corresponding to the second image; and establishing the value of the particular pixel on basis of a first value of a first pixel of the first image if the first motion vector difference is smaller than the second motion vector difference and establishing the value of the particular pixel on basis of a second value of a second pixel of the second image if the second motion vector difference is smaller than the first motion vector difference.

Abstract: A method of determining a maximum optimum clock frequency at which a digital processing system can operate, the method comprising the steps of: generating a clock signal at an initial frequency; increasing said frequency in a step-wise manner and determining the operation of said system each of a selected number of frequencies, until a clock frequency is identified at which said processor does not operate correctly; and identifying a maximum clock frequency at which said system can operate correctly; characterized in that: said maximum clock frequency comprises the frequency immediately previous to the one identified as being one at which said system does not operate correctly; and in that a timing monitor is provided for determining whether or not said system can operate within system timing constraints at each frequency, thereby indicating whether or not said system operates correctly at the respective frequency.

Abstract: A method of performing modular multiplication of integers X and Y to produce a result R, where R=X.Y mod N, in a multiplication engine. X is fragmented into a first plurality of words xn each having a first predetermined number of bits, k and Y is fragmented into a second plurality of words yn each having a second predetermined number of bits, m. Multiples of a word xn of X are derived in a pre calculation circuit and subsequently used to derive products of the word xn of X with each of the plurality of words yn of Y. An intermediate result Rjis calculated as a cumulating sum derived from said pre-calculated multiples and the steps repeated for each successive word of X so as to generate successive intermediate results, Rj, for each of the first plurality of words xn. The final result, R is obtained from the last of the intermediate results Rn?1.

Abstract: A data processing circuit has four signal conductors between a driver and a receiver, and first and second, mutually conducting shield planes. First and second signal conductors form a symmetrical stack in a column between the first and the second plane. Third and fourth signal conductors are arranged substantially midway between the first and the second plane, on mutually opposite sides of the stack. The first, second, third and fourth signal conductors have respective widths so that respective transmission line impedances of transmission lines between each particular one of the first, second, third and fourth conductors and the first and second planes are substantially mutually equal.

Abstract: Consistent with example embodiments a semiconductor device and a method are disclosed for obtaining on a substrate a multilayer structure with a quantum well structure. The quantum well structure comprises a semiconductor layer sandwiched by insulating layers, wherein the material of the insulating layers has preferably a high dielectric constant. In a field effect transistor (FET) the quantum wells function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with molecular beam epitaxy (MBE).

Abstract: The present invention relates to a method and apparatus for detecting voice activity in a communication signal, wherein filter means are provided for estimating or suppressing an offset component of the level of the communication signal. A filter parameter is controlled based on the output of the filter means. Furthermore, the estimation or suppression of the offset component is limited in response to the output of the filter means. The filter means may be based on a non-linear adaptive notch level filter or a noise floor tracking filter. Thereby, the tracking behavior of noise floor estimation to sudden rises in noise floor can be improved and the voice activity detection can work efficiently over a wide dynamic range.

Abstract: Devices (1,2) comprising feedback-less amplifiers (16,19,26,29) that are gain controlled introduce linear relationships between output signals and input signals of the feedback—less amplifiers (16,19,26,29) by providing the feedback—less amplifiers (16,19,26,29) sub-circuits in the form of first transistors (33) operated in their triode regions for receiving input signals and second sub-circuits in the form of second transistors (34) for receiving control signals and third sub-circuits in the form of resistors (35) for generating output signals, whereby the respective first and second and third sub-circuits form a serial path. Second circuits (4) receive gain signals and convert the gain signals into the control signals. The control signals are copies of the gain signals. The second circuits (4) comprise current sources (6) and third and fourth transistors (41,42). The current sources (6) comprise fifth and sixth transistors (61,62).

Abstract: A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.

Abstract: The invention relates to a MEMS resonator comprising a first electrode, a movable element (48) comprising a second electrode, the movable element (48) at least being movable towards the first electrode, the first electrode and the movable element (48) being separated by a gap (46, 47) having sidewalls. According to the invention, the MEMS resonator is characterized in that the gap (46, 47) has been provided with a dielectric layer (60) on at least one of the sidewalls.

Abstract: Methods and apparatus for implementing and operating one or more pseudo-synchronous registers with reduced power consumption, and reduced complexity for transferring data between clock domains. Various embodiments of the present invention replace conventional continuous clocking schemes with a strobe signal that is only generated when a data transfer operation with the one or more pseudo-synchronous registers is to take place. The strobe signal is generated so as to have a duration of one full cycle of the clock signal which defines the clock domain in which the at least one pseudo-synchronous register resides.

Abstract: An apparatus for mapping primitives of a 3D graphics model from a texture space to a screen space. The apparatus includes a texture memory for storing texture maps. A resampler resamples, for each primitive, data from a texture map that corresponds to the primitive to corresponding pixel data defining a portion of a display image that corresponds to the primitive. The texture space resampler and/or the screen space resampler is operative to select a resampling algorithm for performing the resampling from a respective set of at least two distinct resampling algorithms. The selection is done in dependence on a size of the primitive.

Abstract: The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device,—and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device.

Abstract: In a signal processor, a sampling arrangement (SH11, S12, SH13, ADC1) samples at least a first signal (YA) and a second signal (UA, VA) so as to obtain sampled first signal (YD1) and a sampled second signal (UD1, VD1), respectively. A folding compensator (LPF11, LPF12, LPF13, SUB11, SUB12, MUX12) compensates for a folding component in the sampled first signal (YD1) on the basis of a spectral portion of the sampled second signal (UD1, VD1) that is substantially free of components that originate from the second signal (UA, VA).

Abstract: The invention relates to a receiver (1) comprising an amplifier (31-34) for amplifying an antenna signal, which amplifier (31-34) comprises an amplifier input (11a) and an amplifier output (12a,12b), the amplifier input (11a) being a single ended input for receiving the antenna signal, the amplifier output (12a, 12b) being a differential output, and the amplifier (31-34) comprising circuit (41,42) for reducing a common mode input impedance of the amplifier (31-34).

Abstract: An integrated oscillator (10), for an integrated circuit, comprises i) first (CI1) and second (CI2) compensated inverters mounted in series and each comprising first (PI11;PI21) and second (PI12;PI22) plain inverters mounted in parallel and comprising transistors having channel lengths respectively shorter and longer than an optimal channel length, the first compensated inverter (CI1) having input and output terminals respectively connected to first (N1) and second (N2) nodes and the second compensated inverter (CI2) having input and output terminals respectively connected to the second node (N2) and to a third node (N3), ii) a resistor (R) having a chosen resistance value and comprising first and second terminals connected respectively to the first (N1) and second (N2) nodes, and iii) a capacitor (C) comprising first and second terminals connected respectively to the first (N1) and third (N3) nodes, and having a chosen capacitance value to charge and discharge oneself in order to periodically deliver a clock

Abstract: An integrated circuit arrangement has a processor array (2) with processor elements (4) and a memory (6) with memory elements (8) arranged in rows (32) and columns (30). The columns (30) of memory elements (8) are addressed by respective processor elements (4). An input sequencer (14) and feedback path (24) cooperate to reorder input data in the memory (6) to carry out both block and line based processing.

Abstract: To eliminate common-mode components in differential input signals without the necessity of introducing a transformer and a special feedback loop for eliminating common-mode components, a differential amplifier (1) comprises a first input stage (11) for receiving differential input signals comprising common-mode signals and for outputting first differential intermediate signals, a second input stage (12) for inverting the common-mode signals and for combining inverted common-mode signals and the first differential intermediate signals into second differential intermediate signals, and an output stage (13) for receiving the second differential intermediate signals and for outputting differential output signals.