Abstract: A circuit for a contact-free data carrier comprises a first circuit point and a second circuit point for connection to transmission means of the data carrier; and supply voltage generating means, which are connected to the first connection circuit point and comprise a supply voltage circuit point and a reference potential circuit point and are designed to generate, based on the received carrier signal, a first supply voltage that can be tapped at the supply voltage circuit point against the reference potential circuit point; and direct current decoupling means, which are connected between the second circuit point and the reference potential circuit point and are designed to inhibit a direct current flow between the second circuit point and the reference potential circuit point; and current conducting means that are connected between the second circuit point and the reference potential circuit point, wherein the current conducting means are designed for the unidirectional conduction of current from the referen

Abstract: A signal transmitter for generating a wideband RF signal for use in, for example, a 60 GHz wireless area network, wherein a wideband (e.g 4 GHz) baseband signal is divided into a number of sub-signals (14) that can be synthesized in parallel, thereby relaxing the requirements of the mixed-signal and RF blocks. This division can be performed either in time or frequency and one DAC (12) is used for each sub-band (12). Where frequency division multiplexing is used to divide the baseband signal into sub-bands (14) the additional advantage is afforded whereby analogue adjustment of the gain in each sub-band (14) is possible, so as to compensate for wideband frequency selective fading in the channel.

Abstract: A testing circuit has a shift register circuit (76) for storing instruction data for the testing of an integrated circuit core. Each stage of the shift register circuit comprises a first shift register storage element (32) for storing a signal received from a serial input (wsi) and providing it to a serial output (wso) in a scan chain mode of operation, and a second parallel register storage element (38) for storing a signal from the first shift register storage element and providing it to a parallel output in an update mode of operation. The testing circuit further comprises a multiplexer (70) for routing either a serial test input to the serial input (wsi) of the shift register circuit or an additional input (wpi[n]) into the serial input of the shift register circuit (76).

Abstract: A transmitter comprises a power amplifier (PA) with a power supply input (PI) and an output (PAO) to supply a transmission signal (Vo) with an output power (Po). A power supply (PS) has power supply outputs (PSO1, PSO2) to supply a first power supply voltage (PV1) with a first level and a second power supply voltage (PV2) with a second level, higher than the first level. A switching circuit (SC) is arranged between the power supply outputs (PSOI, PSQ2) and the power supply input (PI) to supply a selected one of the first power supply voltage (PV1) or the second power supply voltage (PV2) to the power amplifier (PA). A controller (CO) supplies a control signal to the switching circuit (SC) in response to a first power change command (PC) indicating a first desired level of the output power (Po), to supply the first power supply voltage (PV1) to the power supply input (PI).

Abstract: The present invention relates to an electronic circuit, apparatus and method for monitoring and controlling power consumption. Accordingly, there is provided an electronic circuit, apparatus and method that includes one or more sequential logic elements (12) that are capable of receiving a clock signal (CLK) and an input signal (I) and providing an output signal (O). The sequential logic element (12) further comprises circuitry (20) for monitoring the input and output signals (I, O), and providing a control signal (CS) in response to the input and output signals (I, O), wherein the IC's power consumption is operatively controllable in response to the control signal.

Abstract: The invention provides for a delay fault test circuitry for producing a train of two clock pulses in response to two respective clock signals of different frequency associated with logic circuits to be tested and which are arranged to run at different speeds, and arranged such that the rising edges of the second of the clock pulses are aligned and further including counting means for producing a reference count value, means for initiating the first of the two clock pulses when the said count value reaches a first threshold value, means for ending the first of the two clock pulses when the said count value reaches a second threshold value, means for initiating the second of the two clock pulses when the said count value reaches a third threshold value; means for ending the second of the two clock pulses when the count value reaches a fourth threshold value, wherein the third threshold value is common for both input clock signals and the first, second and fourth threshold values are based on the respective freq

Abstract: A hierarchical memory access control distinguishes between blocks of data that are known to be sequentially accessed, and the contents of each block, which may or may not be sequentially accessed. If the contents of a block are provided in a sequential manner within the block, but the sequence does not correspond to a higher-level sequence, due to a non-zero offset in the start of the sequence within the block, the memory access control is configured to optimize the use of available memory by signaling when the within-block sequence corresponds to the higher-level sequence. While the within-block sequence differs from the higher-level sequence, access to the buffer is limited to the higher-level partitioning of the buffer. When the within-block sequence corresponds to the higher-level sequence, access to the buffer is provided at the within-block partitioning of the buffer.

Abstract: In a data carrier (2) for contactless communication of storage data (SD) with a reader station (1), a recovery device (13) is provided, with which, following an unexpected abort of the storing of storage data (SD) in a memory (11) by virtue of a lack of supply voltage, a valid storage state can be restored in memory (11). For this purpose, any storage locations that are only weakly stored in memory (11) will be read, and the read-out storage data (SD) will be re-stored in the memory (11).

Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of saw paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1, C2, D1, D2) are assigned to each exposure field, each of which control module fields contains at least one optical control module (OCM-A1, OCM-A2, OCM-B1, OCM-B2, OCM-C1, OCM-C2, OCM-D1, OCM-D2) and lies within the exposure field in question and comprises a plurality of control module field sections (A11, A12 . . . AIN and A21, A22 . . . A2N and B11, B12 . . . B1N and B21, B22 . . . B2N and C1N and C2N and D1N and D2N) and is distributed among several lattice grids (3), wherein each control module field section (A11 to D2N) is located in a lattice field and contains at least one control module component (10,11,12,13,14,15,16,17,18).

Abstract: An electronic circuit, in particular a receiver circuit contains a chain of stream processing circuits (10a-c). The stream processing circuits (10a-c) have control parameter inputs for receiving control parameter values. In order to facilitate design of circuits that receive data with a variable block size, a control circuit (14) is included that selects block sizes of blocks of samples in the respective streams of a plurality of the stream processing circuits (10a-c), a control parameter value for each particular block. The control circuit transmits instructions that specify the selected block sizes and control parameter values to local control circuits (11). Each local control circuit is coupled to the control circuit (14) and the control input of a respective corresponding stream processing circuit (10a-c) from the chain.

Abstract: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode.

Abstract: A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be routed to other chips in the multi-chip package. Control signals provided to the first chip control the routing of the JTAG signals to each chip.

Abstract: The invention relates to a system-on-chip apparatus (1), comprising at least two electronic components (2, 3) serving for special purpose functions and a system bus (7) and at least one random access memory (9) that is integrated into the first electronic component (2), located in common on one substrate (8), wherein the system bus (7) connects the electronic components (2, 3) and wherein the random access memory (9) of the first electronic component (2) is time shareable to the second electronic component (3) via said system bus (7), and to a method for operating such a system-on-chip apparatus (1).

Abstract: A method for manufacturing on a substrate (24) a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone (22) in the substrate (24), thereafter forming the floating gate (28) on the substrate (24), thereafter extending the floating gate (28) using polysilicon spacers (40), and thereafter forming the control gate (44) over the floating gate (28) and the polysilicon spacers (40). Such a semiconductor device may be used in flash memory cells or EEPROMs.

Abstract: An integrated circuit (10) comprises a plurality of functional blocks (101, 102, 103), each of the functional blocks (101, 102, 103) being coupled between a first power supply line (110) and a second power supply line (120). A first functional block (101) is coupled to the first power supply line (110) via a first conductive path including a first switch (131) and a second functional block (102) is coupled to the first power supply line (110) via a second conductive path including a second switch (132), the first switch (131) and the second switch (132) being arranged to respectively disconnect the first functional block (101) and the second functional block (102) from the first power supply line (110) for switching said functional blocks (101; 102) from an active mode to a standby mode.

Abstract: A testing circuit has scan chain segments (62,64,60) defined between parallel inputs (wpi[0] . . . wpi[N?1]) and respective parallel outputs (wpo[0] . . . wpo[N?1]). The scan chain segments comprise a bank (62) of cells of a shift register circuit, a core scan chain portion (62), a first bypass path around the core scan chain portion (62) and a second bypass path around the bank (60) of cells of the shift register circuit. This architecture enables loading of data in parallel into the core scan chain, or into the shift register (WBR). In addition, each scan chain segment also has a series latching element (80), and this provides additional testing capability. In particular, the shifting of data between the latching elements (80) can be used to test the bypass paths while the internal or external mode testing is being carried out. This testing can thus be part of a single ATPG procedure.

Abstract: Devices (1) comprising switching amplifiers (2,3) such as class D amplifiers and comprising loads (4) such as loud speakers are provided with controllers (2) for controlling switching circuits (3) for in respective four states introducing respective four voltage signals across the loads (4), which four voltage signals are different from each other. As a result, the switching power in the high frequency domain, which switching power is dissipated in the loads (4), is reduced. The total power consumption is reduced, which results in a longer playing time per battery. The controllers (2) control the switching circuits (3) for pulse width modulating the voltage signals in dependence of input signals and control the switching circuits (3) for in fifth states introducing fifth voltage signals across the loads (4), to further reduce the switching power and the dissipation in the loads (4) and the total power consumption and to further increase the playing time per battery.

Abstract: A subharmonic mixer circuit having an input stage (52) and a current modulating stage (64) is disclosed. The input stage (52) receives an RF input signal (RF+, RF?) at a first frequency and generates output currents (i1, i2) varying in dependence upon the Rf input signal. The current modulating stage (64) comprises a first transistor (Q3) for receiving a first local oscillator signal (LOO) respective and a second transistor (Q4) for receiving a second local oscillator signal (LOI 80), 180 degrees out of phase with the first local oscillator signal, such that a modulating current signal (i0), having twice the local oscillator frequency, is superimposed onto the output currents.

Abstract: A method and unit for substracting quantization noise from a pulse code modulated PCM signal being segmented into frames. For achieving this it is proposed to first calculate for each frame of the PCM signal a quantization noise level Bq according to an equation having parameters including n which indicates a specific sample of the PCM signal, S*min[n] which represents the minimum quantization noise level for a specific sample value s*[n] of the PCM signal, S*max[n] which represents the maximum quantization noise level for the specific sample value s*[n] of the PCM signal, w[n] which represents a window-function and W which represents the number of samples per window. Subsequently, the quantization noise as represented by the quantization noise level Bq has to be substracted from the PCM signal, preferably with the help of a suitable background noise substracting system.

Abstract: A circuit module contains a sub-circuit that is capable of providing a level of performance dependent on the version number that is stored in a version number memory. The version number is passed to the sub-circuit from a write-protected memory to the version memory in the multiplex mode with normal operating signals for the sub-circuit. In one embodiment various commands for the circuit module are received from outside the circuit module and distributed in the circuit module via a communication bus. A watchdog monitors received commands for an update command that commands updating of the version number in the version number memory and if so it passes said update command to the communication bus, replacing a version number in the update command by a version number from the write-protected memory. In another embodiment the version number is passed to the sub-circuit in time-slot multiplexing with the signals that are processed, for example in a blanking period of a video signal that is being processed.