Abstract: The electric device (1, 100) has a body (2, 102) having a resistor (7, 107) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 107) has a first electrical resistance when the phase change material is in the first phase and a second electrical resistance, different from the first electrical resistance, when the phase change material is in the second phase. The body (2, 102) further has a heating element (6, 106) being able to conduct a current for enabling a transition from the first phase to the second phase. The heating element (6, 106) is arranged in parallel with the resistor (7, 107).

Abstract: The method for determining a dielectric layer thickness according to the invention comprises the step of providing an electrically conductive body (11) having a dielectric layer (13) which is separated from the electrically conductive body (11) by at least a further dielectric layer (3) and a surface (15) of which is exposed. Onto the exposed surface (15) an electric charge is deposited thereby inducing an electrical potential difference between the exposed surface (15) and the electrically conductive body (11). An electrical parameter relating to the electrical potential difference is determined and a measurement is performed to obtain additional measurement data relating to a thickness of the dielectric layer (13) and/or to a thickness of the further dielectric layer (3). In this way the thickness of the dielectric layer (13) and/or of the further dielectric layer (3) is determined. The method of manufacturing an electric device (100) comprises this method for determining a dielectric layer thickness.

Abstract: A power converter comprises an inductor (L) and a main switch (M1) having a main current path, the inductor (L) and the main current path are arranged in series to receive a DC-input voltage (VIN). A control circuit (CC) controls on-periods (Ton) and/or off-periods (Toff) of the main switch (M1) to stabilize an output voltage (VO) supplied to a load (LO). The control circuit (CC) further has an input (IN) to receive a measuring signal (MS) to protect the main switch (M1) against situations of overvoltage. A measuring circuit (MC) is coupled to a junction (J1) of the inductor (L) and the main current path to obtain the measuring signal (MS) which is indicative of a voltage across the main current path. Preferably, the measuring circuit (MC) comprises a peak-clamp.

Abstract: The frequency divider for high-frequency clock signal comprises: a shift register (8) having cells (10-13) for storing each bit of an initial word, said cells being series connected in a loop (14), and said shift register being capable of shifting each bit of the initial word from the cell in which it is stored to the next cell in the loop at a rate clocked by the high-frequency clock signal, and wherein an output terminal (6) for outputting a frequency-divided clock signal is connected to the output of one cell of the loop of series-connected cells.

Abstract: A method of detecting frequency errors in a receiver during frame synchronization. A fast synchronization and reliable reception of the data requires a fast determination of frequency errors in the received signal. In CPFSK and OFDM, the frequency offset is even more important because of potential subcarrier interference. The method operates in the time domain and removes the 2p limitation in the phase representation by an unwrap function allowing a precise frequency determination.

Abstract: Analog bidirectional switches (20) comprising a first (1) and a second (2) transistor function badly in case of the signal voltage at an input or an output of the switch (20) exceeding the supply voltage used for operating the switch (20). By providing the switch (20) with a circuit (21), a second control signal (“f”) destined for the second transistor (2) is no longer generated by solely inverting a first control signal (“e”) destined for the first tranistor (1), but is generated in response to the first control signal (“e”) and by taking into account the in/output signal (“z”) at an in/output of the switch (20). The circuit (21) comprises a generator (22) for generating the second control signal (“f”) having either a fixed value or a value of the in/output signal (“z”), and comprises a detector (23) for supplying the in/output signal (“z”) to the generator (22). A further circuit (24) comprises a further generator for generating a backgate signal (“bg”) destined for the second transistor (2).

Abstract: All pointer-based accesses require first that the value contained in a pointer register to be read and then that value be used as an address to the appropriate region in random access memory (RAM). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers, a read access involves multiplexing out of appropriate data for the pointer address from these pointer registers to form a target pointer address.

Abstract: A track and hold circuit (1) comprising:—a linear amplifier (2) receiving a differential analog signal (D+, D?) and being controlled by a first binary clock signal (H+) having a first phase,—the linear amplifier (2) providing a feed-forward input signal substantially equal with the differential analog signal (D+, D?) to a pseudo latch circuit (3) in the first phase of the first binary clock signal (H+), said pseudo latch circuit (3) being controlled by a second binary clock signal (H?) for memorizing the input signal and providing a differential output signal (LD+, LD?) substantially equal with the input signal during a second phase of the first binary clock signal (H?), the second binary clock signal being substantially in antiphase with the first binary clock signal (H+).

Abstract: The invention relates to a method of manufacturing a micro-electromechanical device (10), in which are consecutively deposited on a substrate (1) a first electroconductive layer (2) in which an electrode (2A) is formed, a first electroinsulating layer (3) of a first material, a second electroinsulating layer (4) of a second material different from the first material, and a second electroconductive layer (5) in which a second electrode (5A) lying opposite the first electrode is formed which together with the first electrode (2A) and the first insulating layer (3) forms the device (10), in which after the second conductive layer (5) deposited, the second insulating layer (4) is removed by means of an etching agent which is selective with respect to the material of the second conductive layer (5).

Abstract: A sensor (10) has an output coupled to a first comparator input. A control circuit (18) is arranged to switch from an upward tracking mode to a downward relative level detection mode, to a downward tracking mode, to an upward relative level detection mode and back to the upward tracking mode successively. A first and second digital to analog conversion circuit (14a,b) receive a first and second digital control value from the control circuit (18) respectively.

Abstract: An apparatus and method for random number generation, including a plurality of cross-connected latches 210, 215, 220, 225, providing at least two latch outputs (latch1, latch0) is provided. A first XOR 261 receives the at least two latch outputs (latch0, latch1) as an input, and generates a mistake signal “E” when its inputs do not match from the at least two latch outputs (latch0, latch1) being at different logic states. The mistake signal is compared with a previously stored mistake signal by a second XOR 265 to determine whether to obtain a random bit from a pseudo random stream of bits.

Abstract: In a local oscillator for a tuning arrangement for both TV and FM signals there is substantial risk of parasitic oscillation. A special provision is disclosed for effectively reducing this risk. The special provision is a connection of a damping resistor (R1a) for suppressing parsitic oscillations between ground and a junction (J2) of a parallel LC resonator of the local oscillator.

Abstract: A camera is in the form of a sensor (3) composed of light-sensitive elements arranged in a matrix, and at least a first filtering device (10) for processing the signals issuing from said sensitive elements. The filtering device (10) includes a plurality of linear filters (Fmd1, Fmd2, Fdg1, . . . Fdg6) corresponding to medians and diagonals with respect to the sensor for supplying a plurality of filtering indications. An elimination device (14) eliminates the extreme results of these indications and an estimation device (16) supplyies a valid indication from the non-eliminated indications. Thus, the faulty sensitive elements of the sensor (3) do not degrade the images excessively.

Abstract: An antenna diversity receiver comprises a zero-IF receiver connected to two antennas (102a, 102b) via switches (532, 534). Simultaneous measurement of signal qualities from both antennas is possible by routing signals from the first antenna (102a) via a first mixer (106) and channel filter (116) and routing signals from the second antenna (102b) via a second mixer (108) and channel filter (118). A diversity controller (536) compares the signal qualities received from the antennas (102a, 102b) during a data preamble to select a preferred antenna, then adjusts the switches (532, 534) to route the signals from the preferred antenna to both input mixers (106, 108). The amplifier (104a, 104b) connected to the deselected antenna may be switched off during data reception, thereby minimizing extra power consumption. Such an antenna diversity receiver enables effective antenna selection to be performed, even in systems such as Bluetooth where only a very short preamble is provided for receiver configuration.

Abstract: A charge pump comprises a single voltage multiplier stage (1) which converts an input voltage (VDD) into an output voltage (Vo) under control of a clock signal (Q, Qn; CLKO). An oscillator (2) receives the input voltage (VDD) to generate the clock signal (Q, Qn; CLKO) having a repetition period (Tr1, Tr2) which is substantially proportional to a squared input voltage (VDD2).

Abstract: An increasing number of phases in multiphase converters causes an increase in requirements with respect to the control IC. According to the present invention, instead of deriving a new PWM signal for every single phase of the DC-DC converter, the single phases are clustered into groups (22, 24, 26). Within each group, the converters are operated on the basis of one PWM signal (PW M1, PW M2 . . . PW MN). Advantageously, this may allow to reduce the requirements with respect to the control IC and thus may allow the application of cheaper and smaller control ICs.

Abstract: The multiple-output DC-DC converter comprises an inductor (L) and a main switch (S0) which periodically couples a DC-input voltage (Vin) to the inductor (L). Each one of a multitude of loads (L1, L2, L3) is coupled to the inductor (L) via one of a multitude of output switches (S1, S2, S3). One of a multitude of output voltages (V1, V2, V3) is present across each of the loads (L1, L2, L3). A controller (CO) controls the main switch (S0) and the output switches (S1, S2, S3) in sequences (SE) of cycles (CY). Each one of the cycles (CY1, CY2, CY3) contains an on-phase of the main switch (S0) followed by an on-phase of one of the multitude of output switches (S1, S2, S3). The cycles (CY1, CY2, CY3) have either a predetermined first (minimum) duty cycle (D1) or a second (maximum) duty cycle (D2) which is larger than the first duty cycle (D1).

Abstract: This invention relates to a method (and a corresponding terminal) of detecting a presence of a circuit extending arrangement inserted between a physical interface, connected to a terminal, and a smart card, the physical interface being adapted to receive the smart card, the method comprising the steps of measuring at least one electrical characteristic of the physical interface, and determining whether a circuit extending arrangement, changing at least one characteristic of said physical interface, is coupled to said physical interface on the basis said measurement. In this way, simple and efficient detection of a tampering/spy circuit is provided.

Abstract: A receiver having a variable bit slicer for detecting bits in a demodulated signal, comprises a demodulator (14) for deriving a demodulated bit rate signal, means (36) for storing a plurality of threshold values, each of the threshold values being selectively adjustable, means (28, 38) for selecting the threshold value for comparison with the current bit signal (Sn) in response to a sequence of N bits (where N is at least 2) (Bn-1, Bn-2) received prior to the current bit (Bn) and means (38, 40) for using the current bit to update the selected threshold value. Also disclosed is a method of dc offset correction.

Abstract: The present invention is a method and apparatus for testing random numbers generated by a random number generator in real time. As a series of random numbers are generated, a number of bits that have the value of a predetermined logic value at a specific, predefined range of intervals is determined and then applied to an exponential averaging operation (A). Thereafter, it is determined whether the generated random numbers are predictable by comparing the output of all said exponential operations to their predetermined acceptance range.