Abstract: A data carrier (DC) has a receiving-means configuration (RC) which includes a switching means (S) and a first transmission coil (L1), which can be short-circuited with the aid of the switching means (S), and at least one second transmission coil (L2), which is arranged in series with the first transmission coil (L1), and capacitor configuration (CC), which is arranged in parallel with at least the second transmission coil (L2), the receiving means configuration (RC) being configured to be controllable as regards the value of at least one of its elements comprising the at least one second transmission coil (L2) and the capacitor configuration (CC).

Abstract: The present invention relates to a device (D) and an associated method for the synchronization of a DS-CDMA receiver with a synchronization code being sent periodically and discontinuously by a DS-CDMA transmitter. Said device (D) comprises partial correlation calculation means (PC) for applying partial correlation to the received sequence of data and for providing output correlation signals, transform computation means (FFT8) with half inputs being zeros for applying a transform to said output correlation signals and for providing complex output signals, a square absolute value circuit (SQUARE) for calculating the square of absolute values of said complex output signals, slot-wise non-coherent integration means (INT) for applying a non-coherent integration to said square absolute values, and, selecting means (SELMAX) for selecting a maximum from the integrated values. Thus, with the maximum selected, a slot timing and a frequency offset estimate are determined for the synchronization.

Abstract: A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of multi-bit subfields of a vector operand independently. Debug action is taken if one or more of the multi-bit subfields meet the corresponding conditions.

Abstract: The invention relates to a ferroelectric device (10) with a body (11) comprising a substrate (1) and a ferroelectric layer (2) provided with a connection conductor (3) on a side facing away from the substrate (1), which ferroelectric layer contains an oxygen-free ferroelectric material (2) and is used to form an active electrical element (4), in particular a memory element (4). Such a device forms an attractive non-volatile memory device. In accordance with the invention, a conductive layer (5) is present between the substrate (1) and the ferroelectric layer (2), which conductive layer forms a further connection conductor (5) of the ferroelectric layer (2), and the active electrical element (4) is obtained as a result of the fact that the ferroelectric layer (2) forms a Schottky junction with at least one of the connection conductors (3, 5).

Abstract: To provide a circuit arrangement for controlling a sensor by means of a power supply source which is connected to input terminals of the sensor, and an evaluation circuit which is connected to output terminals of the sensor, by means of which the current consumption of a sensor in the standby state can be reduced in a simple manner, the power supply source (14) is switchable between at least two current levels in dependence upon an output signal level (S) of the sensor (12).

Abstract: The semiconductor device has a security coating with embedded magnetic particles and magnetoresistive sensors. This renders possible a measurement of the impedance of security elements defined by magnetoresistive sensors and security coating. If initial values of the impedance are stored, actual values can be compared therewith to see if the device has not been electrically probed or modified. Such a comparison can be used to check the authenticity of the device.

Abstract: An active tunable filter circuit for use as an integratable active filter in a mobile radio apparatus, comprises an active amplifier circuit (A) including a reactive feedback network including a first tunable element (L1) set to pass with amplification a wanted input signal, and a passive resonant circuit (P) coupled to the active amplifier circuit and including an inductive element (LFB, L3 or L4) and an inactive semiconductor element (FET2, FET3 or FET4) having an interelectrode capacitance which in operation resonates with the inductive element at a harmonic of the wanted signal. In one configuration (FIG. 1) the circuit comprises a band pass filter with amplification and in another configuration (FIG. 6-not shown) the circuit comprises a harmonic notch filter with amplification.

Abstract: A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically partitioned into ‘stripes’, or ‘cyclically sequential’ partitions, and the memory accelerator module includes a latch that is associated with each partition. When a particular partition is accessed, it is loaded into its corresponding latch, and the instructions in the next sequential partition are automatically pre-fetched into their corresponding latch. In this manner, the performance of a sequential-access process will have a known response, because the pre-fetched instructions from the next partition will be in the latch when the program sequences to these instructions. Previously accessed blocks remain in their corresponding latches until the pre-fetch process ‘cycles around’ and overwrites the contents of each sequentially-accessed latch.

Abstract: An erasable and programmable non-volatile cell, comprising a first transistor having a source, a drain and a gate; a floating capacitor having a floating gate and a control gate, said floating gate being connected to said gate of said first transistor; and means to detect the state, whether erased or programmed, of the cell; is characterized in that said means to detect the state of the cell comprises a second transistor having a source, a drain and a gate, said second transistor being complementary to said first transistor and said gate of said second transistor being connected to said floating gate.

Abstract: In a transponder (1) and an integrated circuit (5), the integrated circuit (5) has two circuit sections (18, 19) that are arranged for supply with two supply voltages of different levels (VL-HV, VL-LV), a first rectifier circuit (20) and a limiter stage (21) connected downstream of the first rectifier circuit (20) being provided, from which limiter stage (21) the higher, first supply voltage (VL-HV) for the first circuit section (18) can be picked off, and a second rectifier circuit (23) and a control stage (24) to control said second rectifier circuit (23) being provided, from which second rectifier circuit (23) the lower, second supply voltage (VL-LV) for the second circuit section (19) can be picked off without passing through an intervening limiter stage.

Abstract: A tracking data cell (10) comprising:—a pair of track and hold circuits (1, 1?) coupled to a first multiplexer (5),—a clock signal (H+, H?) being inputted substantially in anti-phase in the respective track and hold circuits (1, 1?) for determining a receipt of a data signal (D+, D?) having a rate, —said track and hold circuits (1, 1?) providing an output signal (O) having a substantially half rate.

Abstract: A voltage regulator configured to receive a supply voltage from a voltage supply and provide a regulated voltage to digital circuitry is provided. The voltage regulator comprises first circuitry configured to inhibit high frequency energy generated by the digital circuitry from transmitting into the voltage supply, second circuitry configured to inhibit low frequency energy generated by the digital circuitry from transmitting into the voltage supply, and third circuitry configured to maintain the regulated voltage at a substantially constant value in response to a current drawn by the digital circuitry.

Abstract: The present invention provides an array (20) of magnetoresistive memory elements (10) provided with at least one data retention indicator device (50). The at least one data retention indicator device (50) comprises a first magnetic element (51) and a second magnetic element (52) each having a pre-set magnetisation direction, the pre-set magnetisation direction of the first and second magnetic elements (51, 52) being different from each other. The first and second magnetic elements (51, 52) are suitable for aligning their magnetisation direction with magnetic field lines of an externally applied magnetic field exceeding a detection threshold value. According to the present invention, a parameter of the at least one data retention indicator device (50) is chosen so as to set the detection threshold value of the externally applied magnetic field to be detected.

Abstract: A VLIW processor comprising a plurality of functional units (1, 3, 5, 7), a distributed register file (9, 11, 13, 15) accessible by the functional units (1, 3, 5, 7), a partially connected communication network (17) for coupling the functional units (1, 3, 5, 7) and selected parts of the distributed register file (9, 11, 13, 15), characterized in that the VLIW processor further comprises a communication device (29) for coupling the functional units (1, 3, 5, 7) and the distributed register file (9, 11, 13, 15).

Abstract: An amplifier bias circuit connectable to an amplifier device, comprising a first sensor device for sensing a first amplifier characteristic and for providing at a first sensor output a bias signal related to the first amplifier characteristic. The circuit further comprises a second sensor device for sensing a second amplifier characteristic and for providing at a second sensor output a bias signal related to the second amplifier characteristic. The first sensor output and second sensor output are each connected to an amplifier connect connectable to a bias input of said amplifier device.

Abstract: Mixer-systems comprising gain-blocks (1-4) and switches (5-8) have a flexibility depending upon their configuration (insight) and are made more flexible (basic idea) by supplying data input signals to the gain-blocks (1-4) and oscillation signals to the switches (5-6) for switching couplings between the gain-blocks (1-4). A switch (5-6) comprises a switch-transistor and a gain-block (1-4) either comprises a gain-block-transistor or comprises five gain-block-transistors for increasing the linearity of the mixer-system. The switches (5-6) have main electrodes which in the balanced situation are all coupled via four impedances (13-16) to the gain-blocks (1-4). In the single ended situation two main electrodes are coupled via two impedances (13,15,18,20) to the gain-blocks (1-4) and two others are coupled directly to the gain-blocks (1-4). By introducing further switches (7-8) parallel to the switches (5-6), harmonics can be suppressed.

Abstract: In an electroacoustic transducer (1), an annular shaped magnet system (14) is provided, enclosing an inner space (22), in which inner space (22) an integrated circuit (31) is accommodated, with the aid of which integrated circuit (31) an electrical signal to be sent to a moving coil (29) of transducer (1) can be amplified.

Abstract: A cross coupled folding circuit comprises a reference voltage circuit to supply m reference voltages, an amplifier circuit to provide control signals, in response to an input signal and to the reference voltages and 2n?I three times cross coupled folding circuits, each of which comprising three differential transistor pairs, said differential transistors pairs being controlled by said control signals and active in a voltage range around a respective one of said reference voltages, with m=3(2??1). In cascade with said 2n?I folding circuits, there are differential transistor pairs in n?1 successive steps 2n?1, 2n—2, 20. To obtain complete folding, switching circuits are provided, cooperating with the transistor pairs in the last 2n?2 steps of the cascade configuration, to supply the respective control signals to those transistors of the respective differential transistor pairs that provide complete folding.

Abstract: The present invention provides a magnetoresistive memory cell (30), comprising a magnetoresistive memory element (31), a first current line (32) and a second current line (33), the first and the second current line (32, 33) crossing each other at a cross-point region but not being in direct contact. According to the invention, a bridging element(34) connects the first and second current lines (32, 33) in the vicinity of the cross-point region. The bridging element (34) is magnetically couplable to the magnetoresistive memory element (31). An advantage of the MRAM architecture according to the present invention is that it allows lower power consumption than prior art devices and high selectivity during writing. The present invention also provides a method of writing a value in a matrix of magnetoresistive memory cells (30) according to the present invention, and a method of manufacturing such magnetoresistive memory cells (30).

Abstract: An circuit arrangement and method for reducing the number of processing loops needed to generate an error correction parameter used in the Montgomery method. An initial input to a processing loop is set to a value equal to the modulus, left shifted one register position. Values of the working register are shifted multiple positions during a single loop iteration, and a shifted result is subtracted and compared to zero to determine subsequent contents of the working register.