Abstract: A magnetic field sensor includes at least two magnetoresistive (MR) sensor elements arranged in a half-bridge configuration. Each of the MR sensor elements includes a magnetic region having a magnetic anisotropy with a resultant magnetization. The magnetic anisotropy is created using an oblique incident deposition (OID) technique, with the magnetic regions being deposited at a nonzero deposition angle relative to a reference line oriented perpendicular to a surface of the magnetic field sensor. A system includes an encoder and the half-bridge configuration of the sensor elements. The encoder produces an external magnetic field, having predetermined magnetic variations in response to motion of the encoder, the magnetic field being detectable by the sensor elements. The resultant magnetization of the sensor elements is aligned by OID in a preferred direction perpendicular to the direction of the external magnetic field instead of utilizing a permanent magnet structure for providing a bias magnetic field.

Abstract: A temperature sensor circuit that includes two banks of bipolar transistors where the bipolar transistors of each bank are coupled in parallel in a current leg of the sensor circuit. The current legs are configured to produce voltages and currents that are dependent upon the temperature sensitivity of the bipolar transistors in the current legs. The sensor circuit includes a controller that, in some embodiments, periodically enables subsets of the bipolar transistors of each of bank during operation.

Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, and first and second amplifiers (e.g., main and peaking amplifiers) integrally formed with the die. Inputs of the first and second amplifiers are electrically coupled to the RF signal input terminal. A plurality of wirebonds is connected between an output of the first amplifier and the combining node structure. An output of the second amplifier is electrically coupled to the combining node structure (e.g., through a conductive path with a negligible phase delay). A phase delay between the outputs of the first and second amplifiers is substantially equal to 90 degrees. The second amplifier may be divided into two amplifier portions that are physically located on opposite sides of the first amplifier.

Abstract: An RF power amplifier includes an amplifier device and a shunt-inductance circuit. The amplifier device includes a substrate, a combining node lead, first and second amplifier dies coupled to the substrate, and first and second output circuits. The first and second amplifier dies are configured to amplify first and second input RF signals, respectively, to produce first and second output RF signals at first and second output terminals, respectively. The first output circuit includes a first inductive path connecting the first output terminal to the lead. The second output circuit includes a second inductive path connecting the second output terminal to the lead. The lead is configured to combine the first and second output RF signals to produce a third output RF signal. The shunt-inductance circuit is coupled between the first output terminal and a ground reference.

Abstract: A level shifter includes a pull-down circuit, a pull-up circuit, a protection circuit, and an output generator. The pull-down circuit is configured to receive input voltages, and generate bias voltages. The input voltages are associated with a voltage domain. The pull-up circuit is configured to receive a supply voltage and generate control voltages. The protection circuit is configured to receive reference voltages, and control the generation of the bias voltages and the control voltages. The output generator is configured to receive at least one of the reference voltages, and at least one of the bias voltages and the control voltages, and generate output voltages that are able to reach minimum and maximum voltage levels of another voltage domain. Further, the output voltages remain unaffected by variations in process, voltage, and temperature.

Abstract: Exemplary aspects are directed to FM-radio circuitries and systems in which, at the receiving end of an FM broadcast transmission, circuitry is used to set the bandwidth for receiving the desired channel of the FM broadcast signal based on measured signal properties of immediately-adjacent channel(s) and based on an inverse relationship between an indication of FM modulation level of the other channel(s) and the amount for which the bandwidth is to be set. FM-signal processing circuitry such as logic/CPU circuitry, then receives the desired channel, including information carried by the FM broadcast signal, in response to setting the bandwidth based on the measured signal properties.

Abstract: In one example, a communications circuit processes an amplitude modulated signal by using a first circuit having signal paths to process an amplitude modulated signal as represented by an in-phase component and by a quadrature component, and by using a second circuit to discern random noise pulses from the quadrature component of the amplitude modulated signal. In response, the second circuit generates an estimate of overall noise representing the random noise pulses in the amplitude modulated signal. In the above and more specific examples, the random noise pulses may appear as pulses which overlap with, in terms of time and bandwidth of frequency spectrum, information of the amplitude modulated signal, and the first and second circuits may be part of an RF radio receiving the amplitude modulated signal from an antenna.

Abstract: Embodiments of a digital step attenuator are disclosed. In an embodiment, a digital step attenuator includes a radio frequency (RF) input, an RF output, an attenuation circuit connected between the RF input and the RF output, a shunt switching circuit connected to the attenuator circuit, and a bypass switching circuit connected between the RF input and the RF output. The bypass switching circuit includes a first bypass transistor, and a second bypass transistor, wherein the first bypass transistor and the second bypass transistor are series connected to each other between the RF input and the RF output, and a bypass shunt transistor connected between the first bypass transistor and the second bypass transistor.

Abstract: A mechanism is provided to remove heat from an integrated circuit (IC) device die by directing heat through a waveguide to a heat sink. Embodiments provide the waveguide mounted on top of a package containing the IC device die. The waveguide is thermally coupled to the IC device die. The waveguide transports the heat to a heat sink coupled to the waveguide and located adjacent to the package on top of a printed circuit board on which the package is mounted. Embodiments provide both thermal dissipation of the generated heat while at the same time maintaining good radio frequency (RF) performance of the waveguide.

Abstract: A mechanism is provided by which a hardware filter on a border router of a wireless personal area network is not overloaded by increasing the probability that the hardware filter will capture all the nodes not on the corresponding WPAN. Network addresses for nodes within a subnet are allocated to have the same multicast address hash value in order to permit router multicast filtering to occur within hardware. Hardware filtering thereby relieves the router processor from performing filtering tasks, reducing resource consumption and decreasing the time used to perform filtering. Embodiments provide this functionality by assigning a unique multicast filter register value to each subnet within a network and allocating network addresses associated with that multicast filter register value through either DHCP or SLAAC address generation.

Abstract: A plurality of memory cells, in which each memory cell includes two corresponding supply terminal inputs, is powered up while applying a voltage differential between the corresponding supply terminal inputs for each of the plurality of memory cells. After powering up, the plurality of memory cells is read and a physically unclonable function (PUF) response is generated from data of the reading.

Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

Abstract: Aspects of the subject disclosure may include, for example, a method in which a selection is made for a first major constituent, a second major constituent and a minor constituent for forming a desired material. The method can include mixing the first major constituent, the second major constituent and the minor constituent in a single mixing step to provide a mixture of constituents. The method can include drying the mixture of constituents to provide a dried mixture of constituents and calcining the dried mixture of constituents to provide a calcinated mixture of constituents. The method can include processing the calcinated mixture of constituents (by a process including vacuum annealing and hot-pressing) to provide a sputtering target. Other embodiments are disclosed.

Abstract: There is described a method of managing memory in an electronic device, the method comprising creating a set of equally sized logical regions in a logical address space, each logical region comprising a plurality of consecutive logical addresses, and mapping a subset of consecutive logical addresses within each logical region to a set of physical addresses within a corresponding physical memory region, the subset of consecutive logical addresses comprising the first logical address within the logical region, said first logical address being mapped to a base address within the corresponding physical memory region. Furthermore, there is described a controller for managing memory in an electronic device and a method of determining a physical memory address in a physical memory region using such a controller.

Abstract: A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form.

Abstract: Various embodiments relate to a method for generating a bit stream in a physical unclonable function (PUF) system, including: receiving a set of values from a plurality of physical devices in the PUF system in a first order; sorting the set of values into a second order; for each of the L highest values, setting a corresponding levelTag value to a first bit value and setting a corresponding usageTag value to a first usage value that indicates that the levelTag for the corresponding value is to be used to generate the bit stream, wherein L is a level setting; for each of the L lowest values, setting a corresponding levelTag value to a second bit value and setting a corresponding usageTag value to the first usage value, wherein the first bit value is different from the second bit value; setting the usageTag value for all other values that are not the highest L values or the lowest L values to a second usage value that indicates that the corresponding value is not to be used to generate the bit stream; generatin

Abstract: A geometric correction system and method for performing geometric correction of a distorted image in an input frame to provide a corrected image in an output frame including a local memory, geometric correction circuitry, a tile reader, and a descriptor memory storing multiple tile descriptors. The tile reader retrieves distorted tile data from the input frame into the local memory for one corrected tile group at a time according to a corresponding tile descriptor. Each tile descriptor identifies distorted tile data to retrieve and distorted tile data to skip from the local memory for the corresponding corrected tile group. The tile descriptor includes a descriptor for each row of local memory area identifying data to be read and data to be skipped for each row. Only the data needed for one or more target tiles is read to reduce memory transfer bandwidth overhead.

Abstract: In accordance with a first aspect of the present disclosure, a radio frequency identification (RFID) transponder is provided, comprising: at least one functional component configured to perform a function of the RFID transponder; a charge pump configured to supply an output voltage to said functional component, wherein said charge pump comprises a plurality of charge pump stages; a charge pump controller configured to control a number of charge pump stages which contribute to the output voltage. In accordance with a second aspect of the present disclosure, a corresponding method of operating an RFID transponder is conceived.

Abstract: A method is provided for executing instructions in a pipelined processor. The method includes receiving a plurality of instructions in the pipelined processor. A first instruction of the plurality of instructions has a first bit field for holding a value for indicating how many times execution of the first instruction is repeated. Also, the value is for indicating how many no operation (NOP) instructions follow a last iteration of the repeated first instruction. The number of repeated instructions plus the number of NOP instructions is equal to the number of pipeline stages in the pipelined processor. In another embodiment, a pipelined data processor is provided for executing the repeating instruction.

Abstract: Embodiments of digital low-dropout (LDO) regulators and methods for operating a digital LDO regulator are described. In one embodiment, a digital LDO regulator includes a clamp circuit configured to generate a clamp voltage in response to an input voltage of the digital LDO regulator, a gate driver circuit configured to generate a drive voltage in response to the input voltage and the clamp voltage, and at least one transistor device configured to generate an output voltage in response to the input voltage and the drive voltage. Other embodiments are also described.