Abstract: As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.

Abstract: A microcontroller comprising a first integrated circuit configured to receive power from a power supply comprising a second integrated circuit via at least one power input terminal and wherein at least one communication terminal provides for communication between the microcontroller and the power supply, wherein the microcontroller is configured to provide for encrypted communication between the power supply and the microcontroller based on a pre-shared encryption key, the encrypted communication configured to provide for authentication of the identity of the power supply and, if the power supply passes the authentication, the microcontroller is configured to operate in a normal mode and receive said power from the power supply, and if the power supply fails authentication, the microcontroller is configured to enter a tamper mode.

Abstract: The disclosure relates to a processing module and associated method for calibrating an object-detection system for a vehicle comprising a plurality of object-detection sensors. The method comprises receiving, from each of a plurality of the object-detection sensors, a value associated with the detection of a marker; and determining a position of each of the object-detection sensors with respect to the vehicle based on the received values associated with the detection of the marker.

Abstract: An apparatus for suppressing parasitic leakage from I/O pins to substrate in floating rail based ESD protection networks is disclosed. In one embodiment, the apparatus includes an integrated circuit (IC) including a conductor, a pin, a first diode coupled between the pin and the conductor, and a first circuit coupled between the conductor and the pin. The first circuit is configured to selectively couple the pin to the conductor based on a voltage on the pin and a voltage on the conductor.

Abstract: An integrated circuit device includes a level shifter circuit with a supply voltage rail to provide a supply voltage, a first pull-up circuit coupled between the supply voltage rail and a first node, a second pull-up circuit coupled between the supply voltage rail and a second node, a first switch including a first terminal coupled to the supply voltage rail, a second terminal coupled to the first node, and a control terminal coupled to the second node, and an inverter including an input terminal coupled to the first node, a voltage supply terminal coupled to the supply voltage, and an output terminal to provide an output voltage from the level shifter circuit.

Abstract: As disclosed herein, a level shift circuit includes devices that are responsive to an ESD signal for placing those devices in a specific condition in response to the ESD signal indicating an ESD event. In some embodiments, the devices are transistors in current paths that are placed in a condition such that during an ESD event, voltage differentials in the current paths across voltage domain boundaries do not damage the circuitry of the level shift circuit. In some embodiments, some of the same devices that are responsive to the ESD event are also responsive to a signal to that detects the absence of a power supply voltage of one of the domains and places those devices in a condition to disable the level shift circuit if the power supply voltage is not present.

Abstract: A single-inductor, multiple-output, DC-DC converter has regulation circuitry that controls switches to alternately charge at least two capacitors associated with at least two DC output voltages via the single inductor from a DC input port. The regulation circuitry determines whether the DC-DC converter is operating in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). In CCM mode, the regulation circuitry regulates the charging duty cycle for a first output voltage and generates the initial charging duty cycle for regulating each other output voltage by scaling the first output voltage duty cycle. In DCM mode, the regulation circuitry independently regulates the charging duty cycles for each output voltage and stores each duty cycle to be used for the next charging period for the same output voltage. The regulation circuitry detects and handles undershoot and overshoot conditions to accelerate recovery at the output ports.

Abstract: A vehicle network system is disclosed. The vehicle network system includes a first controller area network (CAN) bus including a first node and a first secure transceiver and a second CAN bus including a second node and a second secure transceiver, a gateway to enable transmission of a CAN message from the first node to the second node. The vehicle network system also includes an auxiliary communication link to transmit an auxiliary data derived from the CAN message from the first secure transceiver to the second secure transceiver.

Abstract: A system for securing a secret word during a read of the secret word from a read-only memory (ROM) is disclosed. The system includes a memory controller coupled to the ROM and a random number generator coupled to the memory controller. The random number generator is configured to generate a random number. The system further includes a number shuffler coupled to the random number generator and the memory controller. The number shuffler is configured to generate a bit read order based on the random number and the memory controller is configured to read bits of the secret word from the ROM according to the bit read order.

Abstract: Embodiments of a passive buffer circuit and a wideband communication circuit that uses the passive buffer circuit are disclosed. In an embodiment, the passive buffer circuit includes buffer elements connected between input terminals and output terminals that are connected to input terminals of a communication component circuit with a plurality of input transistors. Each of the buffer elements provides a first path with a resistor and a second path with a series-connected capacitor and inductor. The passive buffer circuit further includes current sources connected between the output terminals and at least one fixed voltage and a feedback loop from the input transistors to the current sources to control direct current (DC) voltage at each of the input terminals of the communication component circuit. The feedback loop includes an error amplifier that controls the current sources based on voltages on the input transistors with respect to a reference voltage.

Abstract: A method of making a semiconductor device is provided for depositing, patterning, and developing photoresist (1703, 1704) on an underlying layer located on a backside of a wafer having a frontside on which an integrated circuit die are formed over a shared wafer semiconductor substrate and arranged in a grid, thereby forming a patterned photoresist mask with a unique set of one or more openings which are used to selectively etch the underlying layer to form, on each integrated circuit die, a unique die mark identifier pattern of etched openings in the underlying layer corresponding to the unique set of one or more openings in the patterned photoresist mask (1705), where the patterned photoresist mask is removed (1706) from the backside of the wafer before singulating the wafer to form a plurality of integrated circuit devices (1708) which each include a unique die marking.

Abstract: Aspects of the present disclosure are directed to methods and/or apparatuses involving stations (102, 104, 105) participating in wireless station-to-station communications in which each of a plurality of stations shares a wireless communications channel (101). Information is collected wirelessly (102) from transmissions associated with a first communication protocol and from transmissions associated with a second communication protocol. A current communication environment is dynamically discerned therefrom (102), and used to characterize a dynamic relationship of the collected information, which is indicative of respective usage of the wireless communication channel by data transmitted via the respective protocols. Usage of the channel is allocated (102) for respective communications that use the first and second communication protocols based on the dynamic relationship.

Abstract: In an 802.11be wireless system, a receiving station device signals a packet padding capability in a wireless area network in accordance with an Extremely High Throughput (EHT) communication protocol by constructing a MAC control management frame to include an EHT capability element indicating whether a packet extension value longer than 16 ?s is supported by the receiving station device, where one or more fields in the EHT capability element include (1) a common nominal packet padding field having a plurality of values to signal different packet extension values for use with all transmission constellations, spatial streams Nss, and resource unit (RU) allocations supported by the first STA device, including at least one packet extension value longer than 16 ?s; and/or (2) a PHY packet extension threshold (PPET) field comprising a plurality of PPET values to signal packet extension values including at least one packet extension value longer than 16 ?s.

Abstract: A physically unclonable function (PUF) includes an array of differential PUF bits arranged in rows and columns, wherein each differential bit is located at an intersection of a row and a column, and includes a first PUF cell coupled to a corresponding first bit line and first source line and a second PUF cell coupled to a corresponding second bit line and second source line. The PUF includes a source bias transistor coupled between each corresponding first source line and a first power supply terminal and between each corresponding second source line and the first power supply terminal, wherein a gate electrode of each of the source bias transistors is coupled to a second power supply terminal, and a corresponding set of margin transistors coupled in parallel with each source bias transistor, wherein a gate electrode of each margin transistor is coupled to receive a corresponding margin setting control signal.

Abstract: A method for signal transmission includes generating a sequence of modulated symbols, each modulated symbol including multiple sub-carriers having respective sub-carrier frequencies, by (i) designating a first subset of the sub-carriers to serve as non-pilot sub-carriers, and designating a second subset of the sub-carriers to serve as pilot sub-carriers, (ii) modulating non-pilot information onto the non-pilot sub-carriers, and modulating pilot information onto the pilot sub-carriers, and (iii) in at least some of the symbols, setting the non-pilot sub-carriers to a first power level, and setting one or more of the pilot sub-carriers to a second power level that is higher than the first power level. The sequence of the modulated symbols is transmitted over a communication channel to a receiver.

Abstract: Analog to digital conversion errors caused by non-linearities or other sources of distortion in an analog-to-digital converter are compensated for by use of a machine learning system, such as a neural network. The machine learning system is trained based on simulation or measurement data, which may utilize a reference ADC or a digital training signal representing a reference ADC that has less distortion errors than the analog-to-digital converter. The effect on the analog to digital conversion errors by Process-Voltage-Temperature parameters may be incorporated into the training of the machine learning system.

Abstract: A first communication device determines an amount of data queued at the first communication device for transmission. When a control field is to be generated according to a first format, the first communication device determines a scaling value (SV) and an unscaled value (UV) corresponding to the determined amount of data queued for transmission such that a result of SV multiplied by BV indicates the determined amount of data queued for transmission, and generates the control field to include i) a scaling factor subfield set to indicate the SV, and ii) an unscaled queue size subfield set to indicate the BV. When the control field is to be generated according to a second format, the first communication generates the control field to include a queue size subfield set to indicate the determined amount of data queued for transmission and such that the control field does not include the scaling factor subfield.

Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A gate region includes a conductive material filled in the trench. A drift region having a first conductivity type is formed in the semiconductor substrate adjacent to the second sidewall. A drain region is formed in the drift region and separated from the second sidewall by a first distance. A dielectric layer is formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region. A field plate is formed over the dielectric layer and isolated from the conductive material and the drift region by way of the dielectric layer.

Abstract: An embodiment of a heating system includes a cavity configured to contain a load, a thermal heating system (e.g., a convection, radiant, and/or gas heating system) in fluid communication with the cavity and configured to heat air, and an RF heating system. The RF heating system includes an RF signal source configured to generate an RF signal, first and second electrodes positioned across the cavity and capacitively coupled, a transmission path electrically coupled between the RF signal source and one or more of the first and second electrodes, and a variable impedance matching network electrically coupled along the transmission path between the RF signal source and the one or more electrodes. At least one of the first and second electrodes receives the RF signal and converts the RF signal into electromagnetic energy that is radiated into the cavity.

Abstract: A slew rate control circuit is disclosed. The slew rate control circuit includes an input port to receive an input signal, a transmitter to transmit the input signal to an output port and an impedance control circuit coupled between the transmitter and the output port. The impedance control circuit has an adjustable impedance that is configured to be adjusted during a rise and a fall of the input signal using a trim code and an one shot pulse.