Abstract: A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.

Abstract: A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.

Abstract: A wireless transceiver system includes a transmitter and a receiver. The transmitter includes a digital processor and a self-correction modulator coupled to the digital processor, wherein based upon a calibration correction assessment of an in-phase (I) signal and a quadrature (Q) signal received from the digital processor, the self-correction modulator generates a calibrated modulated signal. The self-correction modulator includes a core modulator and a calibration correction unit. The calibration correction unit is configured to correct an output of the core modulator based upon the calibration correction assessment. The calibration correction unit includes a calibration processing unit and a calibration modulator, wherein the calibration processing unit provides correction quantities that are used to program the calibration modulator to provide the self-corrected modulated signal.

Abstract: Exemplary aspects of the present disclosure involve a system and related method of PLL circuitry in a chirp signaling FMCW system having a variable PLL bandwidth (BW). To adjust the BW, the PLL circuitry may provide for variable capacitance in the circuitry. This capacitance change may allow for a bandwidth for one slope, as used for the acquisition period. The capacitance may then be adjusted to allow for a different bandwidth for another slope which is used to reset the circuitry in preparation for another frequency sweep. Adjusting the PLL BW, via variable capacitance, may be used to mitigate phase noise which can adversely the PLL.

Abstract: Aspects of the disclosure provide methods and an electronic device for wireless communication. A method includes transmitting, by a first transceiver, control packets via a first wireless communication channel using a first radio access technology. The method includes determining, by processing circuitry, a first parameter indicating an interval between transmissions of the control packets. Further, the method includes determining, based on the first parameter, a size limit for packets to be received by a second transceiver that is configured to receive the packets via a second wireless communication channel using a second radio access technology. The method includes transmitting, by the second transceiver, information indicating the size limit over the second channel so that sizes of the packets sent by the second radio access technology are such that the packets are received by the second transceiver in a time period within the interval between the transmissions of the control packets.

Abstract: A system and method for correcting image distortion is provided. The system and method remaps pixel position of distorted images using a combination of radial distortion correction and tangential distortion correction lookup tables consuming less physical memory. The solution conserves both memory and memory access bandwidth. The radial distortion correction lookup table is formed by taking advantage of radial distortion being generally symmetric about a determined optical center of the camera lens. This symmetry allows for use of a quarter LUT for correction in all quadrants of a distorted image. In addition, tangential distortion can be corrected in a symmetric manner that saves memory space as well.

Abstract: The disclosure relates to a dual-interface integrated circuit (IC) card module for use in a dual-interface IC card. Embodiments disclosed include a dual-interface integrated circuit card module (150), the module comprising: a substrate (104) having first and second opposing surfaces; a contact pad (102) on the first surface of the substrate; an integrated circuit (110) on the second surface of the substrate (104), the integrated circuit (110) having electrical connections to the contact pad (102) through the substrate (104); and a pair of antenna pads (108) disposed in recesses (103) in the second surface of the substrate (104) and electrically connected to corresponding antenna connections on the integrated circuit (110).

Abstract: A power management circuit includes an electrical power input for receiving electrical power, a controller, a finite state machine circuit in communication with the controller and a first voltage regulator in communication with the controller and the electrical power input and having a first output connected to a first capacitor for storing electrical power and to first electrical circuitry. The controller is configured to cyclically enable the first voltage regulator to supply current to charge the first capacitor. The finite state machine circuit is configured to interact with the controller to control the duration of a first time period of a cycle over which the first voltage regulator supplies current to charge the first capacitor and to control the duration of a second time period of the cycle over which the first voltage regulator does not supply current to charge the first capacitor and during which electrical current is receivable by said first electrical circuitry from said first capacitor.

Abstract: A dynamic temperature manager of a wireless system determines a threshold temperature defined by one or more operating parameters of the wireless system, the threshold temperature indicating a temperature in response to which power consumption of the wireless system is to be reduced. The dynamic temperature manager receives an indication of a temperature of the wireless system. A determination is made that the temperature exceeds the threshold temperature. The dynamic temperature manager provides an indication to cause a media access control (MAC) processing circuitry of the wireless system to adjust the one or more operating parameters of the wireless system to reduce the power consumption and the temperature of the wireless system based on the determination that the temperature exceeds the threshold temperature.

Abstract: A system-on-chip (SoC) includes a fuse circuit and decoding circuitry. The fuse circuit includes functional fuses, control fuses utilized as the functional fuses, and fuses configured to store override data that indicates an association between the functional fuses and the control fuses utilized as the functional fuses. The decoding circuitry is configured to output configuration data associated with a configuration of the fuse circuit based on the override data and an initial configuration of the fuse circuit. In such a scenario, functional operations of the SoC are executed based on the configuration data. Alternatively, the decoding circuitry is configured to output a set of functional data based on the override data and various functional data stored in the functional fuses and the control fuses utilized as the functional fuses. In such a scenario, the functional operations are executed based on the outputted set of functional data.

Abstract: A method of tie bar removal is provided. The method includes forming a leadframe including a tie bar and a flag. The tie bar extends from a side rail of the leadframe and has a distal portion at an angle different from a plane of the flag. A semiconductor die is attached to the flag of the leadframe. A molding compound encapsulates the semiconductor die, a portion of the leadframe, and the distal portion of the tie bar. The tie bar is separated from the molding compound with an angled cavity remaining in the molding compound.

Abstract: A multiple-path (e.g., Doherty) amplifier includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, first and second amplifiers (e.g., main and peaking amplifiers, or vice versa) integrally formed with the semiconductor die, and a shunt circuit electrically connected between an output of the first amplifier and a ground reference node. Inputs of the first and second amplifier are electrically coupled to the RF signal input terminal, and outputs of the first and second amplifier are electrically coupled to the combining node structure. The shunt circuit includes a shunt inductance and a shunt capacitance coupled in series between the output of the first amplifier and the ground reference node, and the shunt capacitance has a first terminal coupled to the shunt inductance, and a second terminal coupled to the ground reference node.

Abstract: Disclosed is a control circuit for protecting MOSFETs in I/O buffers or other devices from overvoltage damage, especially during power ramp up. The control circuit can perform additional functions. In one embodiment an integrated circuit (IC) includes input/output (I/O) buffers coupled to an output supply voltage terminal that is configured to receive an output supply voltage Vddio. Each of the I/O buffers has a bias voltage generator that is configured to generate a first bias voltage with a magnitude that depends on a control signal; an output stage that receives the first bias voltage, wherein the output stage is configured to drive an I/O pad based upon a data signal received at the I/O buffer. The IC also includes an I/O buffer controller coupled to the I/O buffers and configured to generate the control signal based upon a magnitude of the output supply voltage Vddio.

Abstract: A semiconductor device is disclosed, a substrate structure; a raised source region; a raised drain region; a separation region disposed laterally between the raised source region and the raised drain region; a gate structure, disposed between the raised source region and the raised drain region and above a part of the separation region, the gate structure being spaced apart from the drain region and defining a drain extension region therebetween; a dummy gate structure in the drain extension region; an epitaxial layer, disposed above and in contact with the substrate structure and forming the raised source region, the raised drain region, and a raised region between the gate structure and the dummy gate structure, wherein the raised region between the gate structure and the dummy gate structure is relatively lightly doped to a conductivity of a second conductivity type which is opposite the first conductivity type.

Abstract: A noise suppression circuit includes a resistor-capacitor (RC) filter where a resistive element of the RC filter has a first terminal configured to receive an input data stream and a second terminal coupled to a circuit node Vrc and a capacitive element coupled to the circuit node, a logic gate having an input coupled to the circuit node and an output configured to provide a filtered data stream, and a switch. The switch is configured to short out the resistive element of the RC filter when the input data stream and the filtered data stream are at a same value and not short out the resistive element when the input data stream and the filtered data stream are at different values.

Abstract: In a solid-state heating system, once a load with specific load characteristics has been placed in a heating cavity, a processing unit produces control signals that indicate an excitation signal frequency and one or more phase shifts, which constitute a combination of parameter values. Multiple microwave generation modules produce RF excitation signals characterized by the frequency and the phase shift(s). Multiple microwave energy radiators radiate, into the heating cavity, electromagnetic energy corresponding to RF excitation signals received from the microwave generation modules. Power detection circuitry takes reflected RF power measurements, and the processing unit determines a reflected power indication based on the measurements. The process is repeated for different combinations of the parameter values, and an acceptable combination of parameter values is determined and stored in a memory of the heating system.

Abstract: A packaged integrated circuit includes a photodiode and a memory. The photodiode generates energy when radiation strikes a surface of the photodiode. The memory includes a plurality of non-volatile memory cells and memory control circuitry. The memory control circuitry is configured to perform an operation to change values stored in at least some of the memory cells of the plurality of non-volatile memory cells while being powered by energy generated by the photodiode. An encapsulant at least partially encapsulates the photodiode and the memory, in which the encapsulant blocks radiation from reaching the surface of the photodiode.

Abstract: A method and processor to determine spatial information regarding a vehicle. The method includes receiving at least one initial frame of FMCW radar data including spatial information regarding the vehicle associated with a radar signal reflected back from the vehicle via a surface of at least one stationary object other than the vehicle. The method also includes receiving at least one further frame of FMCW radar data including: spatial information regarding the vehicle associated with a radar signal reflected back from the vehicle via the surface of at least one stationary object other than the vehicle, and spatial information regarding the vehicle associated with a radar signal reflected directly back from the vehicle. The method further includes using the at least one initial frame of radar data to correct for static clutter associated with the at least one stationary object in the at least one further frame of radar data.

Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

Abstract: A testing method and apparatus is disclosed for testing an integrated circuit device (100) which has a dedicated ground bias pad (121) connected across a high voltage electrostatic discharge clamp circuit (123) to a well-driving ground pad (122) by applying a first voltage to the dedicated ground bias pad to bias a wafer substrate (101) while simultaneously applying a second voltage to the well-driving ground pad to bias the well region (103), where the first and second voltage create a stressing voltage across a buried insulator layer (102, 105) in the integrated circuit device so that a screening test can be conducted to screen for a defect (106) in the buried insulator layer by measuring a leakage current.